1 lane, 2 lane, 3 lane processor cost ?
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From: Skybuck Flying on 20 May 2010 10:09 Hello, x86 has usually two operands/parameters like so: mov a, b Why not three ? Why not one ? Maybe it's because multiple lanes would make the processor more costly ? Does the opposite apply as well ? For example a processor could be designed with just one lane to memory which would work as follows: Target <MemoryLocation> Add <Value or Pointer> Sub <Value or Pointer> Jmp <Value or Pointer> The move/copy could be implemented as follows: Source <MemoryLocation> Target <MemoryLocation> Mov or from <Source Memory Location> to <Dest Memory Location> the mov instruction is therefore eradicated. Notice how all new instructions have just one parameter/operand. The instruction always operator on the "target"... except for from/to which set their own source and target. Has such a processor real/in hardware or virtual/in software ever been created ? Would be it more cheap ? Maybe it would even be easier to program ? ;) Bye, Skybuck.
From: James Harris on 20 May 2010 13:13 On 20 May, 15:09, "Skybuck Flying" <IntoTheFut...(a)hotmail.com> wrote: > Hello, > > x86 has usually two operands/parameters like so: > > mov a, b > > Why not three ? Why not one ? Much of x86 design is to achieve upward compatibility with earlier generations but it has added some useful contructions such as addressing modes suitable for loops. And some of the SSE instrictions have, IIRC, three- and four-operand versions. > > Maybe it's because multiple lanes would make the processor more costly ? Costs apply directly to such things as number of transistors and yield rates. However, other design choices have knock-on effects. For example, to increase the number of operands to three requires additional bits in the instruction. This makes the instructions wider which can add pressure to the instruction cache size. > Does the opposite apply as well ? > > For example a processor could be designed with just one lane to memory which > would work as follows: > > Target <MemoryLocation> > Add <Value or Pointer> > Sub <Value or Pointer> > Jmp <Value or Pointer> > > The move/copy could be implemented as follows: > > Source <MemoryLocation> > Target <MemoryLocation> > Mov > > or > > from <Source Memory Location> > to <Dest Memory Location> > > the mov instruction is therefore eradicated. > > Notice how all new instructions have just one parameter/operand. > > The instruction always operator on the "target"... except for from/to which > set their own source and target. > > Has such a processor real/in hardware or virtual/in software ever been > created ? Yes, take a look at the following link and the Number of Operands section. http://en.wikipedia.org/w/index.php?title=Instruction_set&oldid=325648348 The zero- and one-operand forms are particularly interesting. The text of those is: ----- start of quote ----- Number of operands Instruction sets may be categorized by the maximum number of operands (registers, memory locations, or immediate values) explicitly specified in instructions. Some of the operands may also be given implicitly, stored on top of the stack or in an implicit register and the result is counted as well (despite not being an operand). This number is therefore not the same as the arity of the operations. (In the examples that follow, a, b, and c refer to memory addresses, and reg1 and so on refer to machine registers.) * 0-operand (zero address machines) -- these are also called stack machines, and all operations take place using the top one or two positions on the stack. A pure example of a zero-operand machine is taken from the F21 CPU to add two numbers: #a; load; #b; load; add; #c; store. Note that there are seven separate 'instructions' here three of which push an address on the stack. An alternative hybrid approach is to allow load and store instructions (only) to access memory. All other instructions - i.e. operations on data - would have zero operands and operate on the stack. Allowing load and store to specify memory addresses the same addition would be performed as the following which is based on the Transputer: load a; load b; add; store c. * 1-operand (one address machines) -- often called accumulator machines -- include most early computers. Each instruction performs its operation using a single operand specifier. The single accumulator register is implicitsource, destination, or often bothin almost every instruction: load a; add b; store c. ----- End of quote ----- The two machines mentioned in the quote provide real-world implementations. > Would be it more cheap ? > > Maybe it would even be easier to program ? ;) Maybe. In general something regular is easier to program and easier to write compilers for. James
From: MitchAlsup on 20 May 2010 15:51
I suggest rereading chapter 3 in Hennesey and Patterson: Instruction set design, alternatives and principles. Its all in there, from 0 lane stack machines, through 3 operand memory only machines. Mitch |