ADUC7020
in [Design]
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From: John Larkin on 4 Jun 2010 22:34 On Fri, 04 Jun 2010 12:39:47 -0700, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Fri, 04 Jun 2010 15:07:35 -0400, Phil Hobbs ><pcdhSpamMeSenseless(a)electrooptical.net> wrote: > >>On 6/2/2010 12:14 PM, John Larkin wrote: >>> On Wed, 2 Jun 2010 08:58:27 -0700 (PDT), MooseFET<kensmith(a)rahul.net> >>> wrote: >>> >>>> >>>> Is there anyone here who knows all about the ADUC7020? >>>> >>>> I'm about to give up on getting an answer from Analog. >>> >>> Hey, I don't want to hear about your problems... I'm trying to get an >>> answer from Analog Devices about the AD7699! I think I have finally >>> got them to admit that reference drift does *not* explain zero offset >>> TC. >>> >>Hmm. A customer of mine is planning to use that part to digitize very >>low frequency stuff--seismometer and tiltmeter data and so on...could >>you say a bit more about what the issues are? > >I am seeing a huge amount of zero drift with temperature. Chris >Augusta, the guy at ADI who wrote the datasheet, helped me find the >problem. I now owe him beers. > >In bipolar mode, you apply a differential input between a pair of >pins, like IN0 and IN1, pins 16 and 17, for instance. Turns out that >the IN1 pin must be within +-0.1 volts of Vref/2 or the zero TC goes >to hell. It says that on the datasheet, but I missed it somehow. I'd >got too used to pseudo-differential charge-balance ADCs actually >having lots of common-mode rejection. My bad, I guess. > >On my board, I'm using a 2.5 volt bandgap and a C-load follower opamp >to generate the Vcm used by all 16 ADCs. I can change that to a 2.048 >bandgap and get legal again. > >Here's the board: > >http://www.highlandtechnology.com/DSS/V490DS.html > >Now I can crank the accuracy specs up to less embarassing numbers. > >John > Oh, if they plan to run this ADC at 500 KHz, the timing is right on the bleeding edge. Rob has working VHDL if anybody needs it. John |