AMD64: 32bit operations extend to 64 bits.
in [ASM]
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From: David on 4 Jan 2010 17:16 Hello, Pending my debugger question so I can test this stuff out.... Is it correct in my assumption that taken the instruction: shr edx,2 will result in the high 32 bits of rdx being zero so I can turn around and use rdx? Also, would the following affectively zero the high 32 bits of a general register rax: add eax,0 TIA!!
From: BGB / cr88192 on 4 Jan 2010 17:53 "David" <this(a)is.invalid> wrote in message news:uNt0n.319$Ef7.80(a)newsfe07.iad... > Hello, > > Pending my debugger question so I can test this stuff out.... > > Is it correct in my assumption that taken the instruction: > > shr edx,2 > > will result in the high 32 bits of rdx being zero so I can turn around and > use rdx? > > Also, would the following affectively zero the high 32 bits of a general > register rax: > > add eax,0 > yep, the high bits are zeroed with 32-bit operations. note, however, that they are not zeroed with other-sized operations (8 or 16 bit). in many cases, one may need to check particular instruction semantics for maters of zeroing, especially if one gets into cases involving SSE instructions, as not all operations are entirely consistent here. however, zero-extension is generally the case for 32-bit operations involving GPRs. > TIA!! >
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