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From: linnix on 26 May 2010 15:52
On May 26, 12:41 pm, Dombo <do...(a)disposable.invalid> wrote:
> linnix schreef:
>
> > On May 26, 10:18 am, "NMMX" <alan.embedded(a)n_o_s_p_a_m.nmmx.net>
> > wrote:
> >> Hi all,
>
> >> I have a few questions on how to go about generate the correct waveforms
> >> for reading/writing from/to an external flash memory using an AVR
> >> microcontroller.
>
> >> The AVR has enough I/O to allow direct connection between address, data and
> >> control lines. I don't have to worry about counters/latches etc.
>
> >> The AVR is using a 12MHz clock. How do you work out how long each cycle
> >> will take?
>
> > You mean other than 1/12000000 or 0.833333333333333333333333333333ns?
>
> I'm pretty sure he means something other than
> 0.833333333333333333333333333333ns, my guess is about two orders of
> magnitude more than that.

Yes, you are correct. 0.833333333333333333333333333333 microsec.
From: NMMX on 26 May 2010 16:01
>On May 26, 10:18=A0am, "NMMX" <alan.embedded(a)n_o_s_p_a_m.nmmx.net>
>wrote:
>> Hi all,
>>
>> I have a few questions on how to go about generate the correct
waveforms
>> for reading/writing from/to an external flash memory using an AVR
>> microcontroller.
>>
>> The AVR has enough I/O to allow direct connection between address, data
a=
>nd
>> control lines. I don't have to worry about counters/latches etc.
>>
>> The AVR is using a 12MHz clock. How do you work out how long each cycle
>> will take?
>
>You mean other than 1/12000000 or 0.833333333333333333333333333333ns?
>
>>
>> Also with the AVR it seems there can be a delay when doing I/O
operations=
>,
>> there is a sync latch that is half a cycle, does anyone have any
>> information about this?
>
>If the clock pulse is square and the latch is level activated, it will
>latch exactly half a cycle.
>
>>
>> Currently I just insert random nops to delay cycles until it works as
>> expected. However, I would like to be able to work this out properly so
c=
>an
>> write more efficient code.
>
>Can't help you without knowing exactly what you are trying to do.
>
>

Thanks linnix,

The half cycle is the minimum case, worst is one and half cycles. The
datasheet also says that out instruction sets sync latch, however there are
other ways of setting the port value such as sbi/cbi.

I was hoping that someone could explain better how it effects the delay
when setting a port value.

>Can't help you without knowing exactly what you are trying to do.

The AVR is directly connected to the flash. It sets the ports (address,
data, control) in order to read or write from/to the flash memory. My
current code works however I know its only because I have inserted extra
nops to make sure I have the minimum hold/setup times for the waveform.

With better understanding of how long each cycle is, this sync latch issue
I would be able to modify my code to remove these redundant nops as I would
be able to calculate the correct timing.

Regards.

---------------------------------------
Posted through http://www.EmbeddedRelated.com
From: Dombo on 26 May 2010 16:03
linnix schreef:
> On May 26, 12:41 pm, Dombo <do...(a)disposable.invalid> wrote:
>> linnix schreef:
>>
>>> On May 26, 10:18 am, "NMMX" <alan.embedded(a)n_o_s_p_a_m.nmmx.net>
>>> wrote:
>>>> Hi all,
>>>> I have a few questions on how to go about generate the correct waveforms
>>>> for reading/writing from/to an external flash memory using an AVR
>>>> microcontroller.
>>>> The AVR has enough I/O to allow direct connection between address, data and
>>>> control lines. I don't have to worry about counters/latches etc.
>>>> The AVR is using a 12MHz clock. How do you work out how long each cycle
>>>> will take?
>>> You mean other than 1/12000000 or 0.833333333333333333333333333333ns?
>> I'm pretty sure he means something other than
>> 0.833333333333333333333333333333ns, my guess is about two orders of
>> magnitude more than that.
>
> Yes, you are correct. 0.833333333333333333333333333333 microsec.

And the correct answer is.... 83.3 ns!
From: -jg on 26 May 2010 18:04
On May 27, 8:01 am, "NMMX" <alan.embedded(a)n_o_s_p_a_m.nmmx.net> wrote:
> My
> current code works however I know its only because I have inserted extra
> nops to make sure I have the minimum hold/setup times for the waveform.

This is a little mangled.
If you are talking to conventional parallel flash, that should need
minimal timing patches on Read, but it will need care on Write.
ie if you
READ:
Define all address values
Float the IO port
Pull OEN low
[NOP insert point]
Read BUS value
Pull OEN Hi

That will easily meet Address setup time, and leaves
any pipeline effects for bus turnaround.
It's easy to check if you know the expected read value.

Write is going to need a scheme to load a page, or partial page, and
then time, or poll, for the Write completion.
Polling is probably the more revision-safe approach.

-jg

From: Meindert Sprang on 27 May 2010 02:14
"NMMX" <alan.embedded(a)n_o_s_p_a_m.nmmx.net> wrote in message
news:-IOdncrK-Z-b42DWnZ2dnUVZ_jWdnZ2d(a)giganews.com...
>
> The AVR is directly connected to the flash. It sets the ports (address,
> data, control) in order to read or write from/to the flash memory. My
> current code works however I know its only because I have inserted extra
> nops to make sure I have the minimum hold/setup times for the waveform.

If you create the bus cycles manually with a 12MHz AVR, you must have a very
slow flash before you need to insert NOPs to get the timing right. What's
the speed of the flash chip you're using?
To give you an idea: I am currently working with a PIC18 running at 24MHz
(at gun point, I must admit) and the flash has an access time of 100ns. No
NOPs required and the total transfer speed is dead slow at 75kbyte/s....

Meindert


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