Analog neagtive delay generator - please help
in [Basics]
|
Prev: If you’re installing radio communications, data tracking, visual displays or navigation equipment.
Next: Galvanic disconnection with transformer
From: Tim Wescott on 26 Mar 2010 19:07 whit3rd wrote: > On Mar 26, 9:09 am, Daku <dakup...(a)gmail.com> wrote: >> Could some analog guru please help ? Digital circuits can use a delay >> locked loop to generate a negative delay - is there any corresponding >> analog circuit to achieve the same result ? > > Firstly, what is 'delay locked loop'? It is a delay line with a variable tap, or some sort of variable RC delay, that is controlled in a similar manner to a PLL to get controlled delay. They're way popular in FPGAs these days, to de-skew clocks, double clocks (by XORing a clock with a delayed version), have controlled phase differences between clocks, and other useful things that you need if you want to build really, really, really fast logic on a chip that's only really, really fast. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
From: John Larkin on 26 Mar 2010 21:45 On Fri, 26 Mar 2010 09:26:24 -0700, Tim Wescott <tim(a)seemywebsite.now> wrote: >John Larkin wrote: >> On Fri, 26 Mar 2010 09:09:27 -0700 (PDT), Daku <dakupoto(a)gmail.com> >> wrote: >> >>> Could some analog guru please help ? Digital circuits can use a delay >>> locked loop to generate a negative delay - is there any corresponding >>> analog circuit to achieve the same result ? Any hints, suggestions >>> would be invaluable. Thanks in advance for your help. >> >> What kind of signal do you want to delay? If it's a periodic clock, >> all sorts of phase shifters or delay lines will work. A 0.75T delay >> line looks like a -0.25T delay. Or invert phase and delay 0.25, same >> result. >> >> If it's a general signal, it's impossible. >> >> John >> >> >Well, so much for the stock market investment machine I was going to build! Even a small negative delay could be put into a feedback loop to get arbitrary long negative delays, enough to see the Drudge Report a week in advance. John
From: krw on 26 Mar 2010 22:38 On Fri, 26 Mar 2010 15:42:11 -0700 (PDT), whit3rd <whit3rd(a)gmail.com> wrote: >On Mar 26, 9:09�am, Daku <dakup...(a)gmail.com> wrote: >> Could some analog guru please help ? Digital circuits can use a delay >> locked loop to generate a negative delay - is there any corresponding >> analog circuit to achieve the same result ? > >Firstly, what is 'delay locked loop'? It's a delay line in the feed back path of an oscillator. A "digital PLL", if you will. >When one needs a signal and a delayed copy of that signal, one uses >a delay line (simplest is just a long cable). Then, the events >on the signal cable are occurring prior to those on the delay line, >and you can refer timings to the delay-line-output and >call the direct signal 'negative delay'. That's how an >oscilloscope can trigger on a pulse and still show the >lead-up to the pulse on the display.
From: Daku on 27 Mar 2010 00:35 The problem I am trying to solve is : Consider an analog PLL and the reference signal is pure sinusoidal. In a "locked in" mode, the VCO output will be a sinusoidal signal of exactly same frequency as the reference signal, but has an added phase (basically delay), because of the way the VCO works. So is there a way to remove this phase ?? On Mar 26, 9:20 pm, John Larkin <jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: > What kind of signal do you want to delay? If it's a periodic clock, > all sorts of phase shifters or delay lines will work. A 0.75T delay > line looks like a -0.25T delay. Or invert phase and delay 0.25, same > result. > > If it's a general signal, it's impossible. > > John
From: Tim Wescott on 27 Mar 2010 00:48
Daku wrote: > > On Mar 26, 9:20 pm, John Larkin > <jjlar...(a)highNOTlandTHIStechnologyPART.com> wrote: > >> What kind of signal do you want to delay? If it's a periodic clock, >> all sorts of phase shifters or delay lines will work. A 0.75T delay >> line looks like a -0.25T delay. Or invert phase and delay 0.25, same >> result. >> >> If it's a general signal, it's impossible. >> >> John > > The problem I am trying to solve is : > Consider an analog PLL and the reference signal is pure sinusoidal. In > a "locked in" mode, the VCO output will be a sinusoidal signal of > exactly same frequency as the reference signal, but has an added phase > (basically delay), > because of the way the VCO works. So is there a way to remove this > phase ?? > That depends on your phase detector. If you're talking about a classic mixer-style phase detector that returns zero error when the VCO is 90 degrees off from the reference -- yes. So you can solve that, either by making a network that phase shifts the VCO by 90 degrees before applying it to the phase detector, or -- if your reference is also a pure tone -- by using a digital reference detector that returns zero error when the phases match. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com |