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From: Nico Coesel on 12 Aug 2010 12:45
"M. Hamed" <mhelshou(a)hotmail.com> wrote:

>Hello there,
>
>I'm part of a team that has been assigned the task of designing a
>system consisting of a backplane and a number of daughter board. Each
>daughter board will have a large number of chips. The main board will
>need to communicate with one chip at a time but the communication
>lines will go to every single chip and it's up to a controller
>(possibly on the daughter board) to enable each chip individually.
>
>None of us has enough experience with stacks of boards or backplanes.
>We are worried that connecting one signal line to that many boards and
>chips will introduce too many signal integrity problems and
>capacitance that will make it impossible.
>
>We are not sure whether the best topology would be a backplane and a
>bunch of daughter boards connected via edge connectors or a stack of
>boards with each board plugging into the board below it and the bottom
>daughter board connecting to the backplane/motherboard. We think that
>the latter approach would be worse especially for the boards higher up
>in the stack of boards.
>
>Can someone provide some advice over how to go about designing this
>and what could be possible solutions? Are there any established design
>practices? Are there any technical terms we should be looking up or
>certain resources we should be consulting? As I mentioned we don't
>have enough experience with this kind of problem. Most of what we've
>done was single board systems.

First of all you need to determine what kind of bandwidth you need and
how many modules need to be connected.

Another hint: have a power supply on each module and use a 12V central
PSU to distribute power throught the backplane. Also make sure to use
chips that allow for hot-swapping to connect to the backplane.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: Rich Grise on 12 Aug 2010 19:12
On Thu, 12 Aug 2010 16:45:44 +0000, Nico Coesel wrote:

> "M. Hamed" <mhelshou(a)hotmail.com> wrote:
>
>>Hello there,
>>
>>I'm part of a team that has been assigned the task of designing a
>>system consisting of a backplane and a number of daughter board. Each
>>daughter board will have a large number of chips. The main board will
>>need to communicate with one chip at a time but the communication
>>lines will go to every single chip and it's up to a controller
>>(possibly on the daughter board) to enable each chip individually.
>>
>>None of us has enough experience with stacks of boards or backplanes.
>>We are worried that connecting one signal line to that many boards and
>>chips will introduce too many signal integrity problems and
>>capacitance that will make it impossible.
>>
>>We are not sure whether the best topology would be a backplane and a
>>bunch of daughter boards connected via edge connectors or a stack of
>>boards with each board plugging into the board below it and the bottom
>>daughter board connecting to the backplane/motherboard. We think that
>>the latter approach would be worse especially for the boards higher up
>>in the stack of boards.
>>
>>Can someone provide some advice over how to go about designing this
>>and what could be possible solutions? Are there any established design
>>practices? Are there any technical terms we should be looking up or
>>certain resources we should be consulting? As I mentioned we don't
>>have enough experience with this kind of problem. Most of what we've
>>done was single board systems.
>
> First of all you need to determine what kind of bandwidth you need and
> how many modules need to be connected.
>
> Another hint: have a power supply on each module and use a 12V central
> PSU to distribute power throught the backplane. Also make sure to use
> chips that allow for hot-swapping to connect to the backplane.

This sounds like a resurrection of the S-100 bus, which sucked because it
took all of Intel's crappy control signals and spread them on the bus, but
it did account for driving the bus, and terminating and buffering the
signals.

Just make sure your drivers have enough OOMPH, and terminate and buffer
the signals on the daughters; if you have timing concerns that 1/2 nsec
(6 inches) would screw up your synchronicity, then you should probably
look into that new PCI stuff or the kind of technology that they used with
ECL in the Cray and stuff.

Good Luck!
Rich


From: Nico Coesel on 13 Aug 2010 16:37
Rich Grise <richgrise(a)example.net> wrote:

>On Thu, 12 Aug 2010 16:45:44 +0000, Nico Coesel wrote:
>
>> "M. Hamed" <mhelshou(a)hotmail.com> wrote:
>>
>>>Hello there,
>>>
>>>I'm part of a team that has been assigned the task of designing a
>>>system consisting of a backplane and a number of daughter board. Each
>>>daughter board will have a large number of chips. The main board will
>>>need to communicate with one chip at a time but the communication
>>>lines will go to every single chip and it's up to a controller
>>>(possibly on the daughter board) to enable each chip individually.
>>>
>>>None of us has enough experience with stacks of boards or backplanes.
>>>We are worried that connecting one signal line to that many boards and
>>>chips will introduce too many signal integrity problems and
>>>capacitance that will make it impossible.
>>>
>>>We are not sure whether the best topology would be a backplane and a
>>>bunch of daughter boards connected via edge connectors or a stack of
>>>boards with each board plugging into the board below it and the bottom
>>>daughter board connecting to the backplane/motherboard. We think that
>>>the latter approach would be worse especially for the boards higher up
>>>in the stack of boards.
>>>
>>>Can someone provide some advice over how to go about designing this
>>>and what could be possible solutions? Are there any established design
>>>practices? Are there any technical terms we should be looking up or
>>>certain resources we should be consulting? As I mentioned we don't
>>>have enough experience with this kind of problem. Most of what we've
>>>done was single board systems.
>>
>> First of all you need to determine what kind of bandwidth you need and
>> how many modules need to be connected.
>>
>> Another hint: have a power supply on each module and use a 12V central
>> PSU to distribute power throught the backplane. Also make sure to use
>> chips that allow for hot-swapping to connect to the backplane.
>
>This sounds like a resurrection of the S-100 bus, which sucked because it
>took all of Intel's crappy control signals and spread them on the bus, but
>it did account for driving the bus, and terminating and buffering the
>signals.

I don't know about the S-100 bus. I just don't like to put
address+data+control onto a backplane. Too many points of failure.
Async serial (iow: UART) or manchester is much better since those
methods allow for timing errors and are less sensitive to external
influences.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: John Larkin on 13 Aug 2010 17:35
On Thu, 12 Aug 2010 16:12:37 -0700, Rich Grise <richgrise(a)example.net>
wrote:

>On Thu, 12 Aug 2010 16:45:44 +0000, Nico Coesel wrote:
>
>> "M. Hamed" <mhelshou(a)hotmail.com> wrote:
>>
>>>Hello there,
>>>
>>>I'm part of a team that has been assigned the task of designing a
>>>system consisting of a backplane and a number of daughter board. Each
>>>daughter board will have a large number of chips. The main board will
>>>need to communicate with one chip at a time but the communication
>>>lines will go to every single chip and it's up to a controller
>>>(possibly on the daughter board) to enable each chip individually.
>>>
>>>None of us has enough experience with stacks of boards or backplanes.
>>>We are worried that connecting one signal line to that many boards and
>>>chips will introduce too many signal integrity problems and
>>>capacitance that will make it impossible.
>>>
>>>We are not sure whether the best topology would be a backplane and a
>>>bunch of daughter boards connected via edge connectors or a stack of
>>>boards with each board plugging into the board below it and the bottom
>>>daughter board connecting to the backplane/motherboard. We think that
>>>the latter approach would be worse especially for the boards higher up
>>>in the stack of boards.
>>>
>>>Can someone provide some advice over how to go about designing this
>>>and what could be possible solutions? Are there any established design
>>>practices? Are there any technical terms we should be looking up or
>>>certain resources we should be consulting? As I mentioned we don't
>>>have enough experience with this kind of problem. Most of what we've
>>>done was single board systems.
>>
>> First of all you need to determine what kind of bandwidth you need and
>> how many modules need to be connected.
>>
>> Another hint: have a power supply on each module and use a 12V central
>> PSU to distribute power throught the backplane. Also make sure to use
>> chips that allow for hot-swapping to connect to the backplane.
>
>This sounds like a resurrection of the S-100 bus, which sucked because it
>took all of Intel's crappy control signals and spread them on the bus, but
>it did account for driving the bus, and terminating and buffering the
>signals.
>
>Just make sure your drivers have enough OOMPH, and terminate and buffer
>the signals on the daughters; if you have timing concerns that 1/2 nsec
>(6 inches) would screw up your synchronicity, then you should probably
>look into that new PCI stuff or the kind of technology that they used with
>ECL in the Cray and stuff.
>
>Good Luck!
>Rich
>

The '100' in S100 happened because the guy who did it happened to have
a bunch of 100 pin connectors around.

John

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