Big OOO, SpMT, and possible designs (Was Re: Free/Open x86 Sim)
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From: Robert Myers on 21 May 2010 13:02 On May 21, 11:19 am, Andy 'Krazy' Glew <ag-n...(a)patten-glew.net> wrote: > On 5/20/2010 7:02 PM, David Kanter wrote: > > > > > > >> Hmm, I think I am just realizing that we need different metrics, with different acronyms. I want to express the number > >> of outstanding operations. IPC is not a measure of ILP. OOO window size is extreme. A lower number is the number of > >> insructions simultaneously in some stage of execution; more precisely, simultaneously at the same stage of exection. > > >> "SIX"?: simultaneous instructions in execution? "SIF"?: ... in flight? "SMF"?: simultaneous memory operations in > >> flight? > > > What do you mean by 'same stage of execution'? > > > Anyway, I think the concept you are trying to get at is what I'd call > > a 'cross section'. Essentially if you think of the CPU as a physical > > pipeline (or the memory hierarchy as a pipeline), you want the cross > > sectional area. So perhaps the right terms are 'memory cross section' > > and 'instruction cross section'? > > > DK > > Exactly: a cross section. > > I was trying to use "same stage of execution" to filter out pipeline effects. E.g. a machine with a 42 deep pipeline, > that is capable of only one load per cycle, latency of load data to load address of 1 cycle, etc., might be said to have > 42 loads in flight at all time. I.e. a cross section of 42. However, most of that parallelism wuld be due to > instruction fetch effects, not the actual execution parallelism. The use of "cross section" in this context seems not especially apt, as one takes the cross section of a pipe transverse to the pipe. Robert.
From: Andy 'Krazy' Glew on 21 May 2010 21:59 On 5/21/2010 10:02 AM, Robert Myers wrote: > On May 21, 11:19 am, Andy 'Krazy' Glew<ag-n...(a)patten-glew.net> > wrote: >> On 5/20/2010 7:02 PM, David Kanter wrote: >> >> >> >> >> >>>> Hmm, I think I am just realizing that we need different metrics, with different acronyms. I want to express the number >>>> of outstanding operations. IPC is not a measure of ILP. OOO window size is extreme. A lower number is the number of >>>> insructions simultaneously in some stage of execution; more precisely, simultaneously at the same stage of exection. >> >>>> "SIX"?: simultaneous instructions in execution? "SIF"?: ... in flight? "SMF"?: simultaneous memory operations in >>>> flight? >> >>> What do you mean by 'same stage of execution'? >> >>> Anyway, I think the concept you are trying to get at is what I'd call >>> a 'cross section'. Essentially if you think of the CPU as a physical >>> pipeline (or the memory hierarchy as a pipeline), you want the cross >>> sectional area. So perhaps the right terms are 'memory cross section' >>> and 'instruction cross section'? >> >>> DK >> >> Exactly: a cross section. >> >> I was trying to use "same stage of execution" to filter out pipeline effects. E.g. a machine with a 42 deep pipeline, >> that is capable of only one load per cycle, latency of load data to load address of 1 cycle, etc., might be said to have >> 42 loads in flight at all time. I.e. a cross section of 42. However, most of that parallelism wuld be due to >> instruction fetch effects, not the actual execution parallelism. > > The use of "cross section" in this context seems not especially apt, > as one takes the cross section of a pipe transverse to the pipe. But that's exactly what we are talking about: the width, or diameter, of the pipeline that is processing instructions.
From: Robert Myers on 22 May 2010 13:38 On May 21, 9:59 pm, Andy 'Krazy' Glew <ag-n...(a)patten-glew.net> wrote: > On 5/21/2010 10:02 AM, Robert Myers wrote: > > > > > > > On May 21, 11:19 am, Andy 'Krazy' Glew<ag-n...(a)patten-glew.net> > > wrote: > >> On 5/20/2010 7:02 PM, David Kanter wrote: > > >>>> Hmm, I think I am just realizing that we need different metrics, with different acronyms. I want to express the number > >>>> of outstanding operations. IPC is not a measure of ILP. OOO window size is extreme. A lower number is the number of > >>>> insructions simultaneously in some stage of execution; more precisely, simultaneously at the same stage of exection. > > >>>> "SIX"?: simultaneous instructions in execution? "SIF"?: ... in flight? "SMF"?: simultaneous memory operations in > >>>> flight? > > >>> What do you mean by 'same stage of execution'? > > >>> Anyway, I think the concept you are trying to get at is what I'd call > >>> a 'cross section'. Essentially if you think of the CPU as a physical > >>> pipeline (or the memory hierarchy as a pipeline), you want the cross > >>> sectional area. So perhaps the right terms are 'memory cross section' > >>> and 'instruction cross section'? > > >>> DK > > >> Exactly: a cross section. > > >> I was trying to use "same stage of execution" to filter out pipeline effects. E.g. a machine with a 42 deep pipeline, > >> that is capable of only one load per cycle, latency of load data to load address of 1 cycle, etc., might be said to have > >> 42 loads in flight at all time. I.e. a cross section of 42. However, most of that parallelism wuld be due to > >> instruction fetch effects, not the actual execution parallelism. > > > The use of "cross section" in this context seems not especially apt, > > as one takes the cross section of a pipe transverse to the pipe. > > But that's exactly what we are talking about: the width, or diameter, of the pipeline that is processing instructions. But the second dimension that makes it an area and not a length is parallel to the axis of the pipe. If not, I'm confused. I think you want to convey : how many at once and how far apart. Robert.
From: Andy 'Krazy' Glew on 22 May 2010 14:51 On 5/22/2010 10:38 AM, Robert Myers wrote: > On May 21, 9:59 pm, Andy 'Krazy' Glew<ag-n...(a)patten-glew.net> wrote: >> On 5/21/2010 10:02 AM, Robert Myers wrote: >>>> On 5/20/2010 7:02 PM, David Kanter wrote: >>>>> Anyway, I think the concept you are trying to get at is what I'd call >>>>> a 'cross section'. Essentially if you think of the CPU as a physical >>>>> pipeline (or the memory hierarchy as a pipeline), you want the cross >>>>> sectional area. So perhaps the right terms are 'memory cross section' >>>>> and 'instruction cross section'? >> >>>>> DK >> >>>> Exactly: a cross section. >> >>> The use of "cross section" in this context seems not especially apt, >>> as one takes the cross section of a pipe transverse to the pipe. >> >> But that's exactly what we are talking about: the width, or diameter, of the pipeline that is processing instructions. > > But the second dimension that makes it an area and not a length is > parallel to the axis of the pipe. If not, I'm confused. I think you > want to convey : how many at once and how far apart. > > Robert. I think that we may be trying to push the physical analogy too far here. If you think of a computer pipeline as a 1 dimensional structure, or perhaps n=2 dimensional (1 dimension = position in the pipeline, plus the number of instructions at that stage in the pipeline possibly being considered a second dimension), then a n-1 dimensional cutting hyperplane has n=1. In general, in an n-dimensional space, we talk of cross-sections having n-1 dimensions. But, heck, I think of computer pipelines as having 3 or more dimensions. For example: I often think of pipelines as a sequence of buffers connected in some order, with data flowing between them. The buffers are themselves 2-dimensional in planar VLSI. So, cross-dimension might mean the area of silicon occupied by the instructions that are in flight, and executing, in buffers. Or if you don't like that, how about the more traditional pipeline, with an extra dimension being the number of processors in an MP system. We are pushing the physical or spatial analogy too far here. It's just terminology. If David Kanter finds that the term "cross section" helps him understand what the point I am trying to convey - and I think it does - great. If you don't, too bad. Terminology is arbitrary; but it also matters, because it aids understanding. If there is a term that you like, which aids many other folk, I'll use that. Any suggestions? So far we have * "instructions in flight (at the same stage of execution)" * cross-section * how many at once
From: Robert Myers on 22 May 2010 15:46
On May 22, 2:51 pm, Andy 'Krazy' Glew <ag-n...(a)patten-glew.net> wrote: > > I think that we may be trying to push the physical analogy too far here. > > If you think of a computer pipeline as a 1 dimensional structure, or perhaps n=2 dimensional (1 dimension = position in > the pipeline, plus the number of instructions at that stage in the pipeline possibly being considered a second > dimension), then a n-1 dimensional cutting hyperplane has n=1. In general, in an n-dimensional space, we talk of > cross-sections having n-1 dimensions. > > But, heck, I think of computer pipelines as having 3 or more dimensions. For example: > > I often think of pipelines as a sequence of buffers connected in some order, with data flowing between them. The > buffers are themselves 2-dimensional in planar VLSI. So, cross-dimension might mean the area of silicon occupied by the > instructions that are in flight, and executing, in buffers. > > Or if you don't like that, how about the more traditional pipeline, with an extra dimension being the number of > processors in an MP system. > > We are pushing the physical or spatial analogy too far here. It's just terminology. If David Kanter finds that the > term "cross section" helps him understand what the point I am trying to convey - and I think it does - great. If you > don't, too bad. Terminology is arbitrary; but it also matters, because it aids understanding. If there is a term that > you like, which aids many other folk, I'll use that. Any suggestions? > > So far we have > * "instructions in flight (at the same stage of execution)" > * cross-section > * how many at once I try to avoid discussions of terminology, unless I am confused, which, in this case, I am. I'd have to reread the entire discussion, but it seemed to me that you were interested in how much of the instruction stream the parallelism spanned (farthest distance apart in any serial stream). That's a hard concept to include if you're interested in the net flow rate of instructions, for which you *do* want to look at a cross- section (appropriately averaged in time). If you can reach way out into the instruction stream and grab (say) a memory reference, that seems like a more important quality than net flow rate. You can get a high net flow rate with a linpack benchmark and enough of whatever hooked together. That's not very interesting. If I'm just spewing gibberish, please be patient. I *am* a fluid mechanicist. Robert. |