CD4046 Question
in [Design]
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From: Phil Hobbs on 23 Feb 2010 19:40 On 2/23/2010 7:29 PM, Jim Thompson wrote: > On Tue, 23 Feb 2010 18:12:26 -0500, Phil Hobbs > <pcdhSpamMeSenseless(a)electrooptical.net> wrote: > >> On 2/23/2010 5:15 PM, Jim Thompson wrote: >>> On Tue, 23 Feb 2010 17:04:26 -0500, Phil Hobbs >>> <pcdhSpamMeSenseless(a)electrooptical.net> wrote: >>> > [snip] >>>> >>>> With phase-frequency detectors it's pretty easy--the output goes to the >>>> rail when it's out of lock, so a window comparator works well. >>> >>> What output is that? >> >> The filtered PD output, e.g. at the VCO input. When there's a frequency >> error, the 4046's output goes between tristate and one logic level, so >> the integrated output rails and sits there. That's one of the good >> things about it--I've often used it as a lock detector for PLLs whose >> main phase detector was a diode bridge. (My fave is the Mini-Circuits >> MPD-1.) > > So it's not instantaneous? There isn't much sense in a lock detector that's faster than the loop filter. If you're interested in the phase variance, the phase pulses output can be useful, or you can use an auxiliary PD in quadrature. >>>> >>>> The 4046 also has the "phase pulses" output that (very roughly) tells >>>> you what the phase error is, so you can filter that and use a >>>> comparator. I don't think that works as well as the window comparator >>>> method. >>> >>> Measuring something that is exactly zero width is a wee bit tricky. >> >> But you don't need to. You can decide how big a phase variance you're >> willing to tolerate, and set the threshold accordingly. Thought is >> required. > > "Thought is required." ??? > > Crikey! You trying to out snot Larkin ?:-) Nah, I'm nowhere near as big a wildman as he is, and besides, I can't make Cajun red beans and rice. I didn't mean anything by it. Just quit leading with your chin. ;) >>> >>>> >>>> With an XOR gate or diode mixer PD, you need a second PD plus a 90 >>>> degree phase shift. One excellent method is to use a divide-by-4 >>>> Johnson counter (aka walking ring). Run the main PD off one output and >>>> the lock detector off the other. >>>> >>>> Cheers >>>> >>>> Phil Hobbs >>> >>> What you mean is a "close-to-lock" detector is "easy" ?:-) >>> >>> ...Jim Thompson >> >> No. A PLL is in lock when the frequency error is zero, and the variance >> of the phase error is bounded. You obviously haven't spent enough time >> in low SNR situations. ;) >> >> >> Cheers >> >> Phil Hobbs > > I haven't used a PLL for signal detection since the '60's... just > synthesizers since. > > Knowing that a synthesizer is truly locked and still not "wobbling" is > critical to know prior to turning on a transmitter. > > ...Jim Thompson Sure, but a phase variance meter isn't the same as a lock detector, in my language at least. Once the loop is in lock, you can do all sorts of tricks, which you know at least as well as I do. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
From: Jim Thompson on 23 Feb 2010 20:20 On Tue, 23 Feb 2010 19:40:40 -0500, Phil Hobbs <pcdhSpamMeSenseless(a)electrooptical.net> wrote: >On 2/23/2010 7:29 PM, Jim Thompson wrote: >> On Tue, 23 Feb 2010 18:12:26 -0500, Phil Hobbs >> <pcdhSpamMeSenseless(a)electrooptical.net> wrote: >> [snip] >>> But you don't need to. You can decide how big a phase variance you're >>> willing to tolerate, and set the threshold accordingly. Thought is >>> required. >> >> "Thought is required." ??? >> >> Crikey! You trying to out snot Larkin ?:-) > >Nah, I'm nowhere near as big a wildman as he is, and besides, I can't >make Cajun red beans and rice. Trivial. I just tell my wife, who is truly French/Cajun/Dutch blend (and related to every Carter in Kentucky), what I'd like for dinner ;-) > >I didn't mean anything by it. Just quit leading with your chin. ;) I never lead with my chin. Butt of a rifle maybe ;-) > >>>> >>>>> >>>>> With an XOR gate or diode mixer PD, you need a second PD plus a 90 >>>>> degree phase shift. One excellent method is to use a divide-by-4 >>>>> Johnson counter (aka walking ring). Run the main PD off one output and >>>>> the lock detector off the other. >>>>> >>>>> Cheers >>>>> >>>>> Phil Hobbs >>>> >>>> What you mean is a "close-to-lock" detector is "easy" ?:-) >>>> >>>> ...Jim Thompson >>> >>> No. A PLL is in lock when the frequency error is zero, and the variance >>> of the phase error is bounded. You obviously haven't spent enough time >>> in low SNR situations. ;) >>> >>> >>> Cheers >>> >>> Phil Hobbs >> >> I haven't used a PLL for signal detection since the '60's... just >> synthesizers since. TACAN (couldn't remember the other day)... <http://analog-innovations.com/SED/Pat-3644835.pdf> What Gardner himself said couldn't work, when I demonstrated it at a company (name I can't remember) in El Monte, CA, ~1968-69 :-) >> >> Knowing that a synthesizer is truly locked and still not "wobbling" is >> critical to know prior to turning on a transmitter. >> >> ...Jim Thompson > >Sure, but a phase variance meter isn't the same as a lock detector, in >my language at least. Once the loop is in lock, you can do all sorts of >tricks, which you know at least as well as I do. > >Cheers > >Phil Hobbs Indeed. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: Ban on 24 Feb 2010 01:02 Jim Thompson wrote: > On Wed, 24 Feb 2010 00:34:25 +0100, "Ban" <bansuri(a)web.de> wrote: > >>> >> Its about the 4046 or equivalent here not your high performance >> stuff and who says PD2 in a 4046 is an XOR? >> >> ciao Ban >> > > It's shown that way on the data sheet ?? > The datasheet says: Phase comparator 2 is an edge-controlled digital memory network. It consists of four flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers having a common output node. When the p-type or n-type drivers are ON, they pull the output up to VDD or down to VSS respectively. This type of phase comparator only acts on the positive-going edges of the signals at SIGNIN and COMPIN. Therefore, the duty factors of these signals are not of importance.
From: Gerhard Hoffmann on 24 Feb 2010 03:47 Ban wrote: > Jim Thompson wrote: >> On Wed, 24 Feb 2010 00:34:25 +0100, "Ban" <bansuri(a)web.de> wrote: >> >>> Its about the 4046 or equivalent here not your high performance >>> stuff and who says PD2 in a 4046 is an XOR? >>> >>> ciao Ban >>> >> It's shown that way on the data sheet ?? >> > > The datasheet says: > Phase comparator 2 is an edge-controlled digital memory > > network. It consists of four flip-flops, control gating and a > > 3-state output circuit comprising p and n-type drivers > > having a common output node. When the p-type or n-type > > drivers are ON, they pull the output up to VDD or down to > > VSS respectively. This type of phase comparator only acts > > on the positive-going edges of the signals at SIGNIN and > > COMPIN. Therefore, the duty factors of these signals are > > not of importance. Funny how you avoid mentioning PD1. Gerhard
From: Ban on 24 Feb 2010 04:38
Gerhard Hoffmann wrote: > Ban wrote: >> Jim Thompson wrote: >>> On Wed, 24 Feb 2010 00:34:25 +0100, "Ban" <bansuri(a)web.de> wrote: >>> >>>> Its about the 4046 or equivalent here not your high performance >>>> stuff and who says PD2 in a 4046 is an XOR? >>>> >>>> ciao Ban >>>> >>> It's shown that way on the data sheet ?? >>> >> >> The datasheet says: >> Phase comparator 2 is an edge-controlled digital memory >> >> network. It consists of four flip-flops, control gating and a >> >> 3-state output circuit comprising p and n-type drivers >> >> having a common output node. When the p-type or n-type >> >> drivers are ON, they pull the output up to VDD or down to >> >> VSS respectively. This type of phase comparator only acts >> >> on the positive-going edges of the signals at SIGNIN and >> >> COMPIN. Therefore, the duty factors of these signals are >> >> not of importance. > > > > Funny how you avoid mentioning PD1. > phase detector one can not give you a lock indication.and there will be always a phase angle exept at the center frequency, it's an XOR after all. The OP wanted to detect a "locked" condition. ciao Ban |