CMOS analogues switch capacitance
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From: Chris Jones on 16 Oct 2006 16:43 Jim Thompson wrote: > On Sun, 15 Oct 2006 23:02:08 +0100, Chris Jones > <lugnut808(a)nospam.yahoo.com> wrote: > >>Jim Thompson wrote: >> > [snip] >>> >>> The only relatively constant term would be gate capacitance, ESD and >>> MOS body diode capacitances will be all over the place with >>> temperature. >>> >>> ...Jim Thompson >> >> >>One other thing (that you would know well) is that the gate capacitance of >>the MOS devices will depend strongly on the bias (VGS) so it is important >>to measure the calibration channel and the measurement channel with the >>same DC bias and about the same signal amplitude on the switch pins. >> >>Chris > > Nope. I've modeled that situation very carefully. Once a channel is > induced, the gate _capacitance_ is essentially a constant, only the > series resistance varies which, of course, can screw you up royally if > you aren't aware of it. > > Now that I have it characterized I've been using gate capacitance as > bypass capacitors extensively. > > ...Jim Thompson Right, mos devices are nice dense decoupling capacitors, but they are also used as the varactors in RF VCOs because the capacitance from gate to source and drain is much greater when the channel is formed than the capacitance when the channel is not formed. What I was suggesting is that if the drain/source terminals are very close to the positive supply voltage then the NMOS device will be on and the PMOS device will be off, whereas when the source & drain pins are near the negative rail, then the PMOS device will be on and the NMOS device will be off. Because the PMOS device has probably the same oxide thickness but at least double the width of the NMOS device, I would expect that the capacitance would be substantially more when the PMOS device is on than when only the NMOS device is on, and highest of all when both devices are on. Another thing that I have not yet considered is that many analog switch ICs selectively drive the backgate from either the supply rail or the S/D terminals (and hence have lousy charge injection). Depending on how they do this, all sorts of odd things might happen, which you would be in a better position to comment on I expect. Chris
From: Chris Jones on 16 Oct 2006 18:01 Chris Jones wrote: > Jim Thompson wrote: > >> On Sun, 15 Oct 2006 23:02:08 +0100, Chris Jones >> <lugnut808(a)nospam.yahoo.com> wrote: >> >>>Jim Thompson wrote: >>> >> [snip] >>>> >>>> The only relatively constant term would be gate capacitance, ESD and >>>> MOS body diode capacitances will be all over the place with >>>> temperature. >>>> >>>> ...Jim Thompson >>> >>> >>>One other thing (that you would know well) is that the gate capacitance >>>of the MOS devices will depend strongly on the bias (VGS) so it is >>>important to measure the calibration channel and the measurement channel >>>with the same DC bias and about the same signal amplitude on the switch >>>pins. >>> >>>Chris >> >> Nope. I've modeled that situation very carefully. Once a channel is >> induced, the gate _capacitance_ is essentially a constant, only the >> series resistance varies which, of course, can screw you up royally if >> you aren't aware of it. >> >> Now that I have it characterized I've been using gate capacitance as >> bypass capacitors extensively. >> >> ...Jim Thompson > > Right, mos devices are nice dense decoupling capacitors, but they are also > used as the varactors in RF VCOs because the capacitance from gate to > source and drain is much greater when the channel is formed than the > capacitance when the channel is not formed. What I was suggesting is that > if the drain/source terminals are very close to the positive supply > voltage then the NMOS device will be on and the PMOS device will be off, > whereas when the source & drain pins are near the negative rail, then the > PMOS > device will be on and the NMOS device will be off. OOPS!!! other way around, but you get what I mean.... [snip]
From: joseph2k on 18 Oct 2006 23:26 Jim Thompson wrote: > On Sun, 15 Oct 2006 08:47:27 GMT, Robert Baer > <robertbaer(a)earthlink.net> wrote: > >>Jim Thompson wrote: >>> On Sun, 15 Oct 2006 04:09:17 GMT, Robert Baer >>> <robertbaer(a)earthlink.net> wrote: >>> >>> >>>>Jim Thompson wrote: >>>> >>>> >>>>>On Sat, 14 Oct 2006 11:28:57 -0400, John Popelish <jpopelish(a)rica.net> >>>>>wrote: >>>>> >>>>> >>>>> >>>>>>Joe G (Home) wrote: >>>>>> >>>>>> >>>>>>>Hi All, >>>>>>> >>>>>>>I am measuring capacitance in the pF range and I need to switch >>>>>>>monitoring inputs. >>>>>>> >>>>>>>We can calibrate out any constant capacitance.. However >>>>>>> >>>>>>>The 64,000 dollar question is would you expect the input capacitances >>>>>>>of the CMOS switch to be constant over tempreature? >>>>>>> >>>>>>>The devices I have looked at are the better versions of the CMOS 4053 >>>>>>> etc >>>>>>>... a few from NXP (formerly Philips) >>>>>>>http://www.standardics.nxp.com/products/switches/ >>>>>>> >>>>>>> >>>>>>>While there are input capacitance specifications..... there is no >>>>>>>spec on the relationship between input capacitance vs Temp. >>>>>>> >>>>>>> >>>>>>>Would you expect input capacitance to be fairly constant over the >>>>>>>operating temp range? >>>>>> >>>>>>The short answer is that, unless someone has taken great >>>>>>pains to suppress it, everything changes with temperature. >>>>>> >>>>>>I would use an extra section of switch to measure the >>>>>>capacitance of a switch, and subtract the changes of that >>>>>>that from all the other measurements. >>>>> >>>>> >>>>>John, _Very_good_suggestion_! >>>>> >>>>>The only relatively constant term would be gate capacitance, ESD and >>>>>MOS body diode capacitances will be all over the place with >>>>>temperature. >>>>> >>>>> ...Jim Thompson >>>> >>>> DEfine "gate capacitance"; i think it is subject to changes over >>>>temperature. >>> >>> >>> Duh! The gate oxide is GLASS... so its changes are quite small. >>> >>> ...Jim Thompson >> Are you trying to tell me that glass does not expand and contract >>over temperature??? > > No, but the gate capacitance varies trivially compared to the > surrounding junctions. > > ...Jim Thompson There is another issue with CMOS switches operating in low noise or high speed applications. It is not really like capacitance but produces similar effects, it is charge injection. Charge injection is relatively free of temperature effects, but varies some with input voltage and supply voltage. Have you had to design to control it? -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens. --Schiller
From: Jim Thompson on 19 Oct 2006 10:33 On Thu, 19 Oct 2006 03:26:30 GMT, joseph2k <quiettechblue(a)yahoo.com> wrote: >Jim Thompson wrote: > [snip] >> >> ....the gate capacitance varies trivially compared to the >> surrounding junctions. >> >> ...Jim Thompson > >There is another issue with CMOS switches operating in low noise or high >speed applications. It is not really like capacitance but produces similar >effects, it is charge injection. Charge injection is relatively free of >temperature effects, but varies some with input voltage and supply voltage. >Have you had to design to control it? Yes ;-) ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: Joerg on 19 Oct 2006 12:34
Hello Joseph, > > There is another issue with CMOS switches operating in low noise or high > speed applications. It is not really like capacitance but produces similar > effects, it is charge injection. Charge injection is relatively free of > temperature effects, but varies some with input voltage and supply voltage. > Have you had to design to control it? > I guess anybody who ever designed samplers has. It's not always fun though, especially when you find out like I did a few years ago that your favorite quad array has been priced out of the typical BOM budget range :-( However, there is another architecture that seems to not be taught anymore at the colleges: Four fast diodes and a toroid transformer. Ideally a quad but many of those have become expensive/unobtainium so I usually try to get away with pairs. That reduces Ci effects down to almost zilch. -- Regards, Joerg http://www.analogconsultants.com |