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From: Guga on 8 Mar 2007 18:35
Hi guys

i´m looking for some table or any documentation that can contains the
clock cycles (and instruction lenght) of the mnemonics related to
Packed Data, like: ADDPD, ADDPS, CVTTPD2DQ etc.

Someone have a link containing those kind of informations ?

Best Regards,

guga

From: robertwessel2 on 8 Mar 2007 19:06
On Mar 8, 5:35 pm, "Guga" <Guga...(a)gmail.com> wrote:
> Hi guys
>
> i´m looking for some table or any documentation that can contains the
> clock cycles (and instruction lenght) of the mnemonics related to
> Packed Data, like: ADDPD, ADDPS, CVTTPD2DQ etc.
>
> Someone have a link containing those kind of informations ?


The "Intel® 64 and IA-32 Architectures Optimization Reference Manual"
has some of that. Appendix C includes a lot of latency and throughput
information.

http://www.intel.com/design/processor/manuals/248966.pdf

From: //o//annabee on 8 Mar 2007 19:18
På Fri, 09 Mar 2007 00:35:47 +0100, skrev Guga <GugaGTG(a)gmail.com>:

> Hi guys
>
> i´m looking for some table or any documentation that can contains the
> clock cycles (and instruction lenght) of the mnemonics related to
> Packed Data, like: ADDPD, ADDPS, CVTTPD2DQ etc.
>
> Someone have a link containing those kind of informations ?
>
> Best Regards,
>
> guga

Hi Guga.

Why isnt this useful?

<
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26568.pdf
>


From: Guga on 8 Mar 2007 19:42
On Mar 8, 4:06 pm, "robertwess...(a)yahoo.com" <robertwess...(a)yahoo.com>
wrote:
> On Mar 8, 5:35 pm, "Guga" <Guga...(a)gmail.com> wrote:
>
> > Hi guys
>
> > i´m looking for some table or any documentation that can contains the
> > clock cycles (and instruction lenght) of the mnemonics related to
> > Packed Data, like: ADDPD, ADDPS, CVTTPD2DQ etc.
>
> > Someone have a link containing those kind of informations ?
>
> The "Intel® 64 and IA-32 Architectures Optimization Reference Manual"
> has some of that. Appendix C includes a lot of latency and throughput
> information.
>
> http://www.intel.com/design/processor/manuals/248966.pdf



Tks Robert, this seems to be what i ws looking for.. It have the
latency for different processors (Core Duo, Pentium M, etc.)

one question.. on this document it contains a table of "THROUGHPUT"..
but.. i´m unfamiliar with this word. What does "THROUGHPUT" means in
english ?

Best Regards,

Guga


From: randyhyde on 8 Mar 2007 20:08
On Mar 8, 4:42 pm, "Guga" <Guga...(a)gmail.com> wrote:
> On Mar 8, 4:06 pm, "robertwess...(a)yahoo.com" <robertwess...(a)yahoo.com>
> wrote:
>
> > On Mar 8, 5:35 pm, "Guga" <Guga...(a)gmail.com> wrote:
>
> > > Hi guys
>
> > > i´m looking for some table or any documentation that can contains the
> > > clock cycles (and instruction lenght) of the mnemonics related to
> > > Packed Data, like: ADDPD, ADDPS, CVTTPD2DQ etc.
>
> > > Someone have a link containing those kind of informations ?
>
> > The "Intel® 64 and IA-32 Architectures Optimization Reference Manual"
> > has some of that. Appendix C includes a lot of latency and throughput
> > information.
>
> >http://www.intel.com/design/processor/manuals/248966.pdf
>
> Tks Robert, this seems to be what i ws looking for.. It have the
> latency for different processors (Core Duo, Pentium M, etc.)
>
> one question.. on this document it contains a table of "THROUGHPUT"..
> but.. i´m unfamiliar with this word. What does "THROUGHPUT" means in
> english ?
>
> Best Regards,
>
> Guga

Effectively, it means "number of instructions per unit time" (though I
say this without looking at the table in mind, so I'm guessing here
based on the typical usage of this term in computer science).

Throughput is basically a queuing theory term. The more "throughput" a
system has, the more "work" (or whatever is being accomplished by the
system) is done per unit time. For example, in a multiprogrammed OS,
the term "throughput" generally describes how many jobs can be
finished in a given time (or number of calculations, if you want to
get finer-grained). For example, organizing your concurrent jobs so
that they tend to spend about 50% of their time in I/O and 50% in
computation allows you to double your throughput (as one process will
be typically waiting on I/O while the other process is computing, and
vice-versa) in a simplified model of a computer system.

Again, I haven't looked at the table in question, but it probably
describes instruction throughput based on multiple functional units,
stalls, and stuff like that. Coming from a CPU manufacturer, I can
almost guarantee you that this table is *highly* optimistic (most
tables containing timing information present the most optimistic
view). Again, though *I HAVEN'T LOOKED AT THE TABLE*.
Cheers,
Randy Hyde

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