Converting non quadrature signal to quadrature
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From: Clay on 26 Mar 2010 11:01 On Mar 25, 4:00 pm, Tim Wescott <t...(a)seemywebsite.now> wrote: > glen herrmannsfeldt wrote: > > Jerry Avins <j...(a)ieee.org> wrote: > > >>> I have a non quadrature signal at 3 MHz. I need to convert it to > >>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing > >>> rate at the next stage. What do you experts think would be the best > >>> method in terms of resources (for an fpga) or is there much > >>> difference? > > (snip) > > >> You will have to process the same number of samples either way. 1.5M I > >> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz > >> bandwidth, you need 3 M samples/sec. They can be all regular samples, > >> half I and half Q, half I and half dI/dt, or any other set. > > > There might be some cases where quadrature sampling is better, > > though I am not convinced that there are many. > > > 3MHz isn't fast, so speed probably isn't the reason here. > > > In the case where speed is, you can put two ADCs outside the > > FPGA and separately clock the two. (Ignoring problems due to > > non-linearity in the ADCs.) > > > Now, is it better to do the IQ conversion in the analog domain > > and then send it into the FPGA (More analog circuitry, less > > FPGA resources) or just sample and ADC at 3MHz, and do the > > IQ conversion in digital logic? > > > It seems to me that to do it right, you need carefully matched > > analog filters, where it is easy to do in the digital domain > > without worry about matching of filters. > > > -- glen > > Potayto, potahto. > > Mathematically it's the same to do it in analog or digital. Practically > you have all sorts of channel matching issues if you do it in analog, so > if you can get away with it, you'd rather just sample fast and > downconvert digitally. > > 3MHz is very slow these days. > > I'd go as far as to say that if you _did_ have a carrier that was too > fast for all-digital conversion, and unless bandwidth considerations > ruled it out, you'd be better off to do a traditional superhet stage to > a lower IF, filter, and downconvert to baseband from there. > > -- > Tim Wescott > Control system and signal processing consultingwww.wescottdesign.com- Hide quoted text - > > - Show quoted text - Also if instead of trying to implement a 0 degree and a 90 degree set of filters (with overall delays to ensure causality) you can simply design a pair of filters with +- 45 degrees of phase shift. The filters will have impulse responses that are mirrors of each other, have exactly the same amplitude response and if you make the response symmetrical, then half of the coefs become zero. See here: http://www.claysturner.com/dsp/ASG.pdf I've used this technique in receivers and it works quite well. Clay
From: Vladimir Vassilevsky on 26 Mar 2010 11:07 Clay wrote: > On Mar 25, 4:00 pm, Tim Wescott <t...(a)seemywebsite.now> wrote: > >>glen herrmannsfeldt wrote: >> >>>Jerry Avins <j...(a)ieee.org> wrote: >> >>>>>I have a non quadrature signal at 3 MHz. I need to convert it to >>>>>quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing >>>>>rate at the next stage. What do you experts think would be the best >>>>>method in terms of resources (for an fpga) or is there much >>>>>difference? >>> >>>(snip) >> >>>>You will have to process the same number of samples either way. 1.5M I >>>>plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz >>>>bandwidth, you need 3 M samples/sec. They can be all regular samples, >>>>half I and half Q, half I and half dI/dt, or any other set. >> >>>There might be some cases where quadrature sampling is better, >>>though I am not convinced that there are many. >> >>>3MHz isn't fast, so speed probably isn't the reason here. >> >>>In the case where speed is, you can put two ADCs outside the >>>FPGA and separately clock the two. (Ignoring problems due to >>>non-linearity in the ADCs.) >> >>>Now, is it better to do the IQ conversion in the analog domain >>>and then send it into the FPGA (More analog circuitry, less >>>FPGA resources) or just sample and ADC at 3MHz, and do the >>>IQ conversion in digital logic? >> >>>It seems to me that to do it right, you need carefully matched >>>analog filters, where it is easy to do in the digital domain >>>without worry about matching of filters. >> >>>-- glen >> >>Potayto, potahto. >> >>Mathematically it's the same to do it in analog or digital. Practically >>you have all sorts of channel matching issues if you do it in analog, so >>if you can get away with it, you'd rather just sample fast and >>downconvert digitally. >> >>3MHz is very slow these days. >> >>I'd go as far as to say that if you _did_ have a carrier that was too >>fast for all-digital conversion, and unless bandwidth considerations >>ruled it out, you'd be better off to do a traditional superhet stage to >>a lower IF, filter, and downconvert to baseband from there. >> >>-- >>Tim Wescott >>Control system and signal processing consultingwww.wescottdesign.com- Hide quoted text - >> >>- Show quoted text - > > > Also if instead of trying to implement a 0 degree and a 90 degree set > of filters (with overall delays to ensure causality) you can simply > design a pair of filters with +- 45 degrees of phase shift. The > filters will have impulse responses that are mirrors of each other, > have exactly the same amplitude response and if you make the response > symmetrical, then half of the coefs become zero. See here: > > http://www.claysturner.com/dsp/ASG.pdf > > I've used this technique in receivers and it works quite well. > > Clay Also, if the goal is sample rate reduction, the efficient solution could be a 2-band filterbank rather then quadrature. VLV
From: Clay on 26 Mar 2010 11:16 On Mar 26, 11:07 am, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > Clay wrote: > > On Mar 25, 4:00 pm, Tim Wescott <t...(a)seemywebsite.now> wrote: > > >>glen herrmannsfeldt wrote: > > >>>Jerry Avins <j...(a)ieee.org> wrote: > > >>>>>I have a non quadrature signal at 3 MHz. I need to convert it to > >>>>>quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing > >>>>>rate at the next stage. What do you experts think would be the best > >>>>>method in terms of resources (for an fpga) or is there much > >>>>>difference? > > >>>(snip) > > >>>>You will have to process the same number of samples either way. 1.5M I > >>>>plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz > >>>>bandwidth, you need 3 M samples/sec. They can be all regular samples, > >>>>half I and half Q, half I and half dI/dt, or any other set. > > >>>There might be some cases where quadrature sampling is better, > >>>though I am not convinced that there are many. > > >>>3MHz isn't fast, so speed probably isn't the reason here. > > >>>In the case where speed is, you can put two ADCs outside the > >>>FPGA and separately clock the two. (Ignoring problems due to > >>>non-linearity in the ADCs.) > > >>>Now, is it better to do the IQ conversion in the analog domain > >>>and then send it into the FPGA (More analog circuitry, less > >>>FPGA resources) or just sample and ADC at 3MHz, and do the > >>>IQ conversion in digital logic? > > >>>It seems to me that to do it right, you need carefully matched > >>>analog filters, where it is easy to do in the digital domain > >>>without worry about matching of filters. > > >>>-- glen > > >>Potayto, potahto. > > >>Mathematically it's the same to do it in analog or digital. Practically > >>you have all sorts of channel matching issues if you do it in analog, so > >>if you can get away with it, you'd rather just sample fast and > >>downconvert digitally. > > >>3MHz is very slow these days. > > >>I'd go as far as to say that if you _did_ have a carrier that was too > >>fast for all-digital conversion, and unless bandwidth considerations > >>ruled it out, you'd be better off to do a traditional superhet stage to > >>a lower IF, filter, and downconvert to baseband from there. > > >>-- > >>Tim Wescott > >>Control system and signal processing consultingwww.wescottdesign.com-Hide quoted text - > > >>- Show quoted text - > > > Also if instead of trying to implement a 0 degree and a 90 degree set > > of filters (with overall delays to ensure causality) you can simply > > design a pair of filters with +- 45 degrees of phase shift. The > > filters will have impulse responses that are mirrors of each other, > > have exactly the same amplitude response and if you make the response > > symmetrical, then half of the coefs become zero. See here: > > >http://www.claysturner.com/dsp/ASG.pdf > > > I've used this technique in receivers and it works quite well. > > > Clay > > Also, if the goal is sample rate reduction, the efficient solution could > be a 2-band filterbank rather then quadrature. > > VLV- Hide quoted text - > > - Show quoted text - As Tim alluded to, it all depends on what the OP plans to do with his signal. Clay
From: Jerry Avins on 26 Mar 2010 11:31 Clay wrote: > On Mar 26, 11:07 am, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: >> Clay wrote: >>> On Mar 25, 4:00 pm, Tim Wescott <t...(a)seemywebsite.now> wrote: >>>> glen herrmannsfeldt wrote: >>>>> Jerry Avins <j...(a)ieee.org> wrote: >>>>>>> I have a non quadrature signal at 3 MHz. I need to convert it to >>>>>>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing >>>>>>> rate at the next stage. What do you experts think would be the best >>>>>>> method in terms of resources (for an fpga) or is there much >>>>>>> difference? >>>>> (snip) >>>>>> You will have to process the same number of samples either way. 1.5M I >>>>>> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz >>>>>> bandwidth, you need 3 M samples/sec. They can be all regular samples, >>>>>> half I and half Q, half I and half dI/dt, or any other set. >>>>> There might be some cases where quadrature sampling is better, >>>>> though I am not convinced that there are many. >>>>> 3MHz isn't fast, so speed probably isn't the reason here. >>>>> In the case where speed is, you can put two ADCs outside the >>>>> FPGA and separately clock the two. (Ignoring problems due to >>>>> non-linearity in the ADCs.) >>>>> Now, is it better to do the IQ conversion in the analog domain >>>>> and then send it into the FPGA (More analog circuitry, less >>>>> FPGA resources) or just sample and ADC at 3MHz, and do the >>>>> IQ conversion in digital logic? >>>>> It seems to me that to do it right, you need carefully matched >>>>> analog filters, where it is easy to do in the digital domain >>>>> without worry about matching of filters. >>>>> -- glen >>>> Potayto, potahto. >>>> Mathematically it's the same to do it in analog or digital. Practically >>>> you have all sorts of channel matching issues if you do it in analog, so >>>> if you can get away with it, you'd rather just sample fast and >>>> downconvert digitally. >>>> 3MHz is very slow these days. >>>> I'd go as far as to say that if you _did_ have a carrier that was too >>>> fast for all-digital conversion, and unless bandwidth considerations >>>> ruled it out, you'd be better off to do a traditional superhet stage to >>>> a lower IF, filter, and downconvert to baseband from there. >>>> -- >>>> Tim Wescott >>>> Control system and signal processing consultingwww.wescottdesign.com-Hide quoted text - >>>> - Show quoted text - >>> Also if instead of trying to implement a 0 degree and a 90 degree set >>> of filters (with overall delays to ensure causality) you can simply >>> design a pair of filters with +- 45 degrees of phase shift. The >>> filters will have impulse responses that are mirrors of each other, >>> have exactly the same amplitude response and if you make the response >>> symmetrical, then half of the coefs become zero. See here: >>> http://www.claysturner.com/dsp/ASG.pdf >>> I've used this technique in receivers and it works quite well. >>> Clay >> Also, if the goal is sample rate reduction, the efficient solution could >> be a 2-band filterbank rather then quadrature. >> >> VLV- Hide quoted text - >> >> - Show quoted text - > > As Tim alluded to, it all depends on what the OP plans to do with his > signal. We need to hear from Bob again in order to proceed usefully. Jerry -- Discovery consists of seeing what everybody has seen, and thinking what nobody has thought. .. Albert Szent-Gyorgi �����������������������������������������������������������������������
From: Bob on 27 Mar 2010 19:02
On 26 Mar, 15:31, Jerry Avins <j...(a)ieee.org> wrote: > Clay wrote: > > On Mar 26, 11:07 am, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote: > >> Clay wrote: > >>> On Mar 25, 4:00 pm, Tim Wescott <t...(a)seemywebsite.now> wrote: > >>>> glen herrmannsfeldt wrote: > >>>>> Jerry Avins <j...(a)ieee.org> wrote: > >>>>>>> I have a non quadrature signal at 3 MHz. I need to convert it to > >>>>>>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing > >>>>>>> rate at the next stage. What do you experts think would be the best > >>>>>>> method in terms of resources (for an fpga) or is there much > >>>>>>> difference? > >>>>> (snip) > >>>>>> You will have to process the same number of samples either way. 1.5M I > >>>>>> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz > >>>>>> bandwidth, you need 3 M samples/sec. They can be all regular samples, > >>>>>> half I and half Q, half I and half dI/dt, or any other set. > >>>>> There might be some cases where quadrature sampling is better, > >>>>> though I am not convinced that there are many. > >>>>> 3MHz isn't fast, so speed probably isn't the reason here. > >>>>> In the case where speed is, you can put two ADCs outside the > >>>>> FPGA and separately clock the two. (Ignoring problems due to > >>>>> non-linearity in the ADCs.) > >>>>> Now, is it better to do the IQ conversion in the analog domain > >>>>> and then send it into the FPGA (More analog circuitry, less > >>>>> FPGA resources) or just sample and ADC at 3MHz, and do the > >>>>> IQ conversion in digital logic? > >>>>> It seems to me that to do it right, you need carefully matched > >>>>> analog filters, where it is easy to do in the digital domain > >>>>> without worry about matching of filters. > >>>>> -- glen > >>>> Potayto, potahto. > >>>> Mathematically it's the same to do it in analog or digital. Practically > >>>> you have all sorts of channel matching issues if you do it in analog, so > >>>> if you can get away with it, you'd rather just sample fast and > >>>> downconvert digitally. > >>>> 3MHz is very slow these days. > >>>> I'd go as far as to say that if you _did_ have a carrier that was too > >>>> fast for all-digital conversion, and unless bandwidth considerations > >>>> ruled it out, you'd be better off to do a traditional superhet stage to > >>>> a lower IF, filter, and downconvert to baseband from there. > >>>> -- > >>>> Tim Wescott > >>>> Control system and signal processing consultingwww.wescottdesign.com-Hidequoted text - > >>>> - Show quoted text - > >>> Also if instead of trying to implement a 0 degree and a 90 degree set > >>> of filters (with overall delays to ensure causality) you can simply > >>> design a pair of filters with +- 45 degrees of phase shift. The > >>> filters will have impulse responses that are mirrors of each other, > >>> have exactly the same amplitude response and if you make the response > >>> symmetrical, then half of the coefs become zero. See here: > >>>http://www.claysturner.com/dsp/ASG.pdf > >>> I've used this technique in receivers and it works quite well. > >>> Clay > >> Also, if the goal is sample rate reduction, the efficient solution could > >> be a 2-band filterbank rather then quadrature. > > >> VLV- Hide quoted text - > > >> - Show quoted text - > > > As Tim alluded to, it all depends on what the OP plans to do with his > > signal. > > We need to hear from Bob again in order to proceed usefully. > > Jerry > -- > Discovery consists of seeing what everybody has seen, and thinking what > nobody has thought. .. Albert Szent-Gyorgi > ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ Hi, Apolgies for not replying and thanking you all for your feedback. I had to take a few days away from work. Anyway, here's what i've got.... The signal at 3 Mhz COFDM data (using a 2048 pt IFFT). The 3 MHz IF is non quadrature. I want to get it into quadrature format to that I can feed it into a FFT. An added benefit of this is that I can also half the sampling rate. All of the signal processing will be done in an FPGA so I was just trying to find out what method would be the most efficient to implement. I've never used a HT in a project before but it would seem more efficient as multiplying by cos and sine method will require a filter on the output of each branch. Any feedback, suggestions is much appreciated. Many Thanks Bob |