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From: Les Cargill on 15 Jun 2010 12:12
glen herrmannsfeldt wrote:
> Vladimir Vassilevsky<nospam(a)nowhere.com> wrote:
> (snip)
>
>> Thanks for the link. Interesting reading; although in the real world
>> they rarely give out *any* jitter specs for digital parts. Yes, jitter
>> is crucial in Class D; and this is one of the reasons why naive digital
>> amplifiers have mediocre performance. Other area where it matters is the
>> RF signal generation.
>
> This reminds me of the stories 30 years ago that Class D audio
> amplifiers at higher powers would become popular and affordable
> in a short number of years. Now, 30 years later, I hear even
> less about them. Now that we have much better high-power
> transistors, presumably better for both analog and digital
> designs, why is it that Class D never caught on.
>
> (Especially with the "digital is always better" mindset
> that so many have now.)
>
> -- glen


To the contrary, Class D is making real inroads in the musical
instrument space. It has good SWAP properties, principally
W ( weight).

http://www.zzounds.com/item--CWNXLS2500
http://www.guitarcenter.com/Ampeg-SVT-7PRO-1000W-Class-D-Bass-Amp-Head-105771281-i1509690.gc
http://www.markbass.it/products.php?lingua=en&cat=1&vedi=139

(some may not be exactly Class D, but they're all "digital")

--
Les Cargill

From: Andreas Huennebeck on 15 Jun 2010 12:29
steveu wrote:

>>Vladimir Vassilevsky <nospam(a)nowhere.com> wrote:
>>(snip)
>>
>>> Thanks for the link. Interesting reading; although in the real world
>>> they rarely give out *any* jitter specs for digital parts. Yes, jitter
>>> is crucial in Class D; and this is one of the reasons why naive digital
>>> amplifiers have mediocre performance. Other area where it matters is the
>>> RF signal generation.
>>
>>This reminds me of the stories 30 years ago that Class D audio
>>amplifiers at higher powers would become popular and affordable
>>in a short number of years. Now, 30 years later, I hear even
>>less about them. Now that we have much better high-power
>>transistors, presumably better for both analog and digital
>>designs, why is it that Class D never caught on.

Class D is heavily used for professional power amplifiers.

>>(Especially with the "digital is always better" mindset
>>that so many have now.)
>
> Never caught on? What do you think is inside all those slimline home
> theatre boxes that can genuinely put out hundreds of watts RMS without
> melting?

Well, hundreds of Watts are nothing compared to professional audio
power amplifiers used for PA purposes. Powersofts K20 can output
18 kW out of an 2HE 19" housing with a weight of 12 kg:
http://www.powersoft.it/download_get.php?obj=772

The full analog Peavey CS-800 power amplifier I used in the eighties
had 3 HE, a weight of 20 kg and an output of 800W:
http://www.peavey.com/media/pdf/manuals/80300991.pdf

bye
Andreas
--
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From: Mark on 15 Jun 2010 17:34
On Jun 14, 12:30 am, "crasic" <trueurssian(a)n_o_s_p_a_m.gmail.com>
wrote:
> >"Or let the DPLL run as open loop"
>
> >Do you mean if you feed a constant to your NCO, whatever that may be?
> >If that's the case, then your problem is your reference clock.  This is
> >backed up by your results with that Stanford Research Systems function
> >generator -- your DPLL will see it's reference clock as "truth" even if
> >it's jittery.  Give it a jittery reference clock and feed it the World's
> >Cleanest Signal as input and it'll see jitter in that input and "clean"
> >it right up.
> >Tim Wescott
> >Control system and signal processing consulting
> >www.wescottdesign.com
>
> This DPLL design runs at a frequency set at with an output divider, it is
> essentially a pulse-steal design that adds or subtracts fast clock pulses
> to the base frequency. The capture range for a 100MHz clock is
> approximately 0.1f_set so with the center frequency of ~700Khz we get a
> 8Khz bandpass.
>
> If the signal is outside the lockrange or there is no signal applied the
> pll runs at its open loop frequency set by the divider.
>
> >To begin with: FPGA doesn't mate with low jitter. No matter what
> >filtering is, you can expect jitter in ~100ps range, due to coupling on
> >the crystal. This is rather poor performance. If you need better then
> >that, do a specialized analog circuit.
>
> >Vladimir Vassilevsky
> >DSP and Mixed Signal Design Consultant
> >http://www.abvolt.com
>
> The end design will have some additional digital circuitry on the board in
> the form of an ADC and control circuitry so if there are any digital
> non-fpga solutions that could supplement our fpga filter I'm open to it. We
> are trying to replace specialized (power hungry and expensive as well!)
> analog circuitry with a digital solution so going back to it would be
> pretty redundant!
>
> Could we potentially expect better performance with a programmable logic
> chip instead of an FPGA?
>
> The clock source is a generic crystal generator. Unfortunately I didn't
> have the chance to measure the clock jitter and measuring it now through
> the fpga results in some crazy readings (~1hz at 50 Mhz, or 100 times worse
> than our pll output jitter)

I'm going to ask the OP a basic question at this point for
clarification...

What do you mean by DPLL

I can think of these possibilities:

1) A PLL implemented on an FPGA with digital PD and counters but with
an ANALOG VCO?

2) A PLL implemented with an NCO feeding a DAC and reconstruction
filter creating an anlaog output?

3) A PLL implemented with an NCO where the output is represented by
digital data i.e. an 8 bit wide word for example?

4) something else?

Depending upon your answer, the jitter may be fundamentally inherent
in the operation or it may be due to crosstalk noise etc...

Mark
From: crasic on 15 Jun 2010 19:58

>
>I'm going to ask the OP a basic question at this point for
>clarification...
>
>What do you mean by DPLL
>
>I can think of these possibilities:
>
>1) A PLL implemented on an FPGA with digital PD and counters but with
>an ANALOG VCO?
>
>2) A PLL implemented with an NCO feeding a DAC and reconstruction
>filter creating an anlaog output?
>
>3) A PLL implemented with an NCO where the output is represented by
>digital data i.e. an 8 bit wide word for example?
>
>4) something else?
>
>Depending upon your answer, the jitter may be fundamentally inherent
>in the operation or it may be due to crosstalk noise etc...
>
> Mark
>

Option 4.

By DPLL I mean an entirely digital PLL working with 1 bit binary signals,
We feed it a jittery square signal as a our input signal, There is a binary
phase detector, a loop filter consisting of two up/down counters in a
clever arrangement. The output of the NCO is produced with a constant value
divider of the system clock (thus setting the center frequency of the
bandpass) and the loop filter either inhibits or adds fast clock pulses to
the divider, thus "pulling" the frequency away from the center Luckily the
application we are using this for requires a ~10% duty cycle square wave,
so we require no sine wave regeneration after the loop and we just take the
output of the nco for jitter analysis.


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