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From: N_Cook on 21 Apr 2010 03:20
N_Cook <diverse(a)tcp.co.uk> wrote in message
news:hqjqsm$dhj$1(a)news.eternal-september.org...
> Chris Tansit <tansi(a)keyweb.com> wrote in message
> news:4bcd6a51$0$10914$c3e8da3(a)news.astraweb.com...
> > N_Cook said..
> > >clocks presumably related sum and diff fashion with the
> > >crystals 22.579200 and 24.57600 the CLK3 seems to come
> > >from the USB chip with a 12MHz crystal associated
> > >with it, will have to explore the Cypress datasheet
> >
> > So no luck on the reset? It has stored config somewhere right?
> > If so it has to have some way of resetting a config then.
> >
> > I'd still go with a flash but I would be hesitant to do that
> > without resetting first (if possible).
> > I've found most resets codes are unpublished.
> > Try to find out who the service agents were for them as well.
> >
> > Two more things about the firmware.
> > If it does allow USB boot recovery (e.g. the firmware fails at some
> > point in post) it is either going to fix the problem 100% or due
> > to an underlined hardware problem do nothing.
> > Hopefully if its truly a proper boot recovery it works before the
> > code interfaces to the hardware.
> >
> > I think either way software or a hardware hang flashing it
> > will not make you worse off if its your only option.
> >
> >
> >
>
> CLK3 , not from the USB chip, comes from VCO o/p of U3, a 74HCT4046 ,
whose
> sig in comes from U29 an 04 inverter whose input comes from pin33 of the
> CPLD functional blocks, which is firmly stuck logic H so vicious circle of
> inactivity.
> Incidently TP4 of 8 is the only one with any activity on , one of the
approx
> 22MHz clocks.
> Will have to leave exploring this for a while and get back to bread and
> butter work, but any suggestions for hardware checking in the meantime,
> welcome
>
>

From the R&C of the 4046 CLK3 must be about 200KHz, I wonder what would
happen feeding 200KHz or so into the PLL ? something to try on next powering
up


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