Prev: FHSS Detection with Spec Analyzer
Next: Last Call for Papers Reminder (extended): The World Congress on Engineering WCE 2010
From: Jim Stewart on 22 Mar 2010 13:46
rickman wrote:

snip..

> I wonder how long it will be before we give up on schematics
> altogether and just write pin lists or net lists?

After I'm retired I hope. A well drawn schematic is a
thing of beauty, helping techs to troubleshoot and
customers to understand a product.

You could also ask when mechanical engineers will stop
using fab drawings and just send the data as G codes.
From: rickman on 22 Mar 2010 13:52
On Mar 22, 1:46 pm, Jim Stewart <jstew...(a)jkmicro.com> wrote:
> rickman wrote:
>
> snip..
>
> > I wonder how long it will be before we give up on schematics
> > altogether and just write pin lists or net lists?
>
> After I'm retired I hope.  A well drawn schematic is a
> thing of beauty, helping techs to troubleshoot and
> customers to understand a product.
>
> You could also ask when mechanical engineers will stop
> using fab drawings and just send the data as G codes.

I guess if you have an analog design with a lot of small components a
schematic is good, but for many digital designs there is almost no
point. Look inside any number of modern products and you see one, two
or three large IC packages with lots of traces between them and few
smaller components. The schematics for these products are horrendous,
often much less clear than a simple pin list. Its not that they were
drawn badly, but that it is impossible to draw a 300+ pin part with
much utility. Even by breaking the part into sections it still ends
up being a pin list with a box around it.

I'll grant that analog designs can gain from schematic, but many of
the digital ones are pointless when drawn.

Rick
From: glen herrmannsfeldt on 22 Mar 2010 14:21
In comp.arch.fpga rickman <gnuarm(a)gmail.com> wrote:
(snip)

> Yes, Mentor bought them some time ago and I believe it is still a
> product, but with a different name. Everyone still uses schematics
> for board level design, so the tools will always be there. Although
> to a large extent, even schematics are really just pin lists.

Some time ago, I was wondering about using Verilog for PC board design.

One reason was the idea of taking an old circuit design and implementing
it on a new PC board, but also the whole thing in an FPGA. If both
could be done from the same Verilog, it seemed easier...
(I mostly write structural Verilog, that is, continuous assignment,
with a minimal amount of behavioral Verilog.)

> When I plop an FPGA on the drawing page I am treating it like a pin
> connection list tying each pin (with its pin name) to a short net with
> its net name. The other end of the connection is almost always on a
> different page with the same net name/pin name connection list. The
> fact that the pin names are inside a box and have numbers doesn't
> really make it anything much different from a pin connection table.

And that list could be in the form of Verilog continuous assignment.
That seems a little less obvious for power and ground, though.

> I wonder how long it will be before we give up on schematics
> altogether and just write pin lists or net lists? The only real
> advantage to a schematic from what I have seen is that our minds are
> pretty good at remembering things like orientation around a dial. So
> the component box becomes a watch face, if you will, and we can more
> easily remember that signal foo is in the upper right hand corner than
> we can remember that it is two thirds down in the pin list.

With BGA packaging, though, that doesn't seem so important.

It does seem interesting that many have gone away from schematic
capture for logic design, but do they still use it for PC design?

-- glen
From: glen herrmannsfeldt on 22 Mar 2010 14:23
In comp.arch.fpga Peter <nospam(a)nospam9876.com> wrote:
(snip)

> IMHO functionality is much more obvious from a schematic.

There are netlist to schematic programs. They never work quite
as well as you wish, but sometimes good enough.

> Less so, I admit, if the design is just a load of random digital
> logic.

-- glen
From: glen herrmannsfeldt on 22 Mar 2010 14:27
In comp.arch.fpga Jim Stewart <jstewart(a)jkmicro.com> wrote:
(snip)

> After I'm retired I hope. A well drawn schematic is a
> thing of beauty, helping techs to troubleshoot and
> customers to understand a product.

But some things just get too big to do that way. Would you
really like to see the schemtic for the Itanium chip?

> You could also ask when mechanical engineers will stop
> using fab drawings and just send the data as G codes.

There is the story about the design of the Boeing 777, all done
on computers. When the designers saw the actual airplane, they
were surprised by how big it was. They had been looking at it all
those years on computer monitors. I suppose in previous designs,
that parts would be constructed along the way, looked at by
designers, and changed as needed. That may have been done much
less in the case of the 777.

-- glen
First  |  Prev  |  Next  |  Last
Pages: 1 2 3
Prev: FHSS Detection with Spec Analyzer
Next: Last Call for Papers Reminder (extended): The World Congress on Engineering WCE 2010