First Next-Gen CELL Processor: 2 PPEs - 32 SPEs - at least 1 Teraflop
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From: AirRaid on 7 Dec 2006 14:03 http://www.beyond3d.com/forum/showthread.php?t=36335 latest Cell Roadmap http://img445.imageshack.us/img445/7706/cell2007pw6.jpg "During a recent event IBM has unveiled a few details on Cell roadmap.As you can see Cell will be manufactured at 65nm during next year and a next gen version of the chip is expected around 2010 featuring 2PPE and 32 SPEs (45nm manufacturing technology)." _______________________________________________________________________________ this backs Jim Kahle (IBM's Chief Cell Architect) recent claim that they'd be aiming for 1 TeraFlop performance on a single chip using 32 SPEs http://blogs.mercurynews.com/aei/2006/10/the_playstation.html "JK: For us to extrapolate. We will push the number of special processing units. By 2010, we will shoot for a teraflop on a chip. I think it establishes there is a roadmap. We want to invest in it. For those that want to invest in the software, it shows that there is life in this architecture as we continue to move forward. DT: Right now you're at 200 gigaflops? JK: We're in the low 200s now. DT : So that is five times faster by 2010? JK: Four or five times faster. Yes, you basically need about 32 special processing units."
From: jsavard on 9 Dec 2006 08:37 AirRaid wrote: > this backs Jim Kahle (IBM's Chief Cell Architect) recent claim that > they'd be aiming for 1 TeraFlop performance on a single chip using 32 > SPEs What I want to know is if they're ever going to make a chip that concentrates on *double precision* (64-bit) floating-point performance. John Savard
From: John Dallman on 9 Dec 2006 12:13 In article <1165671427.572529.41970(a)f1g2000cwa.googlegroups.com>, jsavard(a)ecn.ab.ca () wrote: > What I want to know is if they're ever going to make a chip that > concentrates on *double precision* (64-bit) floating-point > performance. Unlikely while they're concentrating on graphics and audio. And while CELL design team concentrates in those areas, it's unlikely to get take-up in the areas that require double precision. Chicken, egg. --- John Dallman jgd(a)cix.co.uk "Any sufficiently advanced technology is indistinguishable from a well-rigged demo"
From: mike on 9 Dec 2006 16:31 "John Dallman" <jgd(a)cix.co.uk> wrote in message news:memo.20061209171321.2468B(a)jgd.compulink.co.uk... | In article <1165671427.572529.41970(a)f1g2000cwa.googlegroups.com>, | jsavard(a)ecn.ab.ca () wrote: | | > What I want to know is if they're ever going to make a chip that | > concentrates on *double precision* (64-bit) floating-point | > performance. | | Unlikely while they're concentrating on graphics and audio. And while | CELL design team concentrates in those areas, it's unlikely to get | take-up in the areas that require double precision. Chicken, egg. | | --- | John Dallman jgd(a)cix.co.uk | "Any sufficiently advanced technology is indistinguishable from a | well-rigged demo" I agree with your prediction of the likely impact of economics. However, this thread triggered an interesting thought. What if IBM abstracted out the SPE interface logic and management software (once it is perfected) to allow third parties to re-use the Cell's high-level design with different specialized SPE instruction sets? Just as they re-use the PowerPC processor architecture on several projects, they could re-use the cell multi-processor extensions to the PPC. The new SPE's could be mini-PPC machines or 64 bit vector floating point engines or IP protocol engines, or compression / de-compression engines, or encryption engines, etc. Mike Sicilian
From: Jason Lee Eckhardt on 9 Dec 2006 16:32
In article <1165671427.572529.41970(a)f1g2000cwa.googlegroups.com>, <jsavard(a)ecn.ab.ca> wrote: >AirRaid wrote: >> this backs Jim Kahle (IBM's Chief Cell Architect) recent claim that >> they'd be aiming for 1 TeraFlop performance on a single chip using 32 >> SPEs > >What I want to know is if they're ever going to make a chip that >concentrates on *double precision* (64-bit) floating-point performance. Yes, they will. Just yesterday at a lecture at Rice University, Andy White of LANL discussed the RoadRunner system being developed around Opteron and Cell. As part of the talk, he showed a roadmap for Cell which has an enhanced version scheduled for early 2008 with better double-precision performance (~100 GFLOP/s). That is the one that will be in the production RoadRunner, if I understood him correctly. Even with the current Cell (~15 DP GFLOP/s), Andy said they were getting 5X speed-up on Sweep3D (hand tuned for Cell) over Opteron. Sweep3D is the core of one of their large production codes and uses double precision for all FP. That is good DP performance. He mentioned that 2-3 other important production apps were expected to do well on Cell, though they had done only the preliminary analysis and not the actual ports yet. |