Floating point DSPs
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From: HardySpicer on 6 Jul 2010 18:33 For floating point arithmetic how much faster is an add/subtract than a multiply/accumulate? (percentage wise). Hardy
From: Raymond Toy on 6 Jul 2010 18:48 On 7/6/10 6:33 PM, HardySpicer wrote: > For floating point arithmetic how much faster is an add/subtract than > a multiply/accumulate? (percentage wise). Probably depends on the chip. The last time I used a floating point dsp (C30!) all floating point ops (add, sub, mul, mac) finished in a single cycle. (I think.) Ray
From: Jerry Avins on 6 Jul 2010 19:01 On 7/6/2010 6:33 PM, HardySpicer wrote: > For floating point arithmetic how much faster is an add/subtract than > a multiply/accumulate? (percentage wise). It depends on the chip. Done in software, multiplication is often faster than addition. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
From: steveu on 6 Jul 2010 23:05 >On 7/6/10 6:33 PM, HardySpicer wrote: >> For floating point arithmetic how much faster is an add/subtract than >> a multiply/accumulate? (percentage wise). > >Probably depends on the chip. The last time I used a floating point dsp >(C30!) all floating point ops (add, sub, mul, mac) finished in a single >cycle. (I think.) It could issue a new floating point instruction each cycle, but each instruction took a number of cycles to move through the pipeline, and pop out the end. I've never seen a floating point unit that attempted to complete the instructions in a single cycle. It would be extremely inefficient. Steve
From: Al Clark on 7 Jul 2010 00:33 Raymond Toy <toy.raymond(a)gmail.com> wrote in news:i10bse$h90$1(a)news.eternal- september.org: > On 7/6/10 6:33 PM, HardySpicer wrote: >> For floating point arithmetic how much faster is an add/subtract than >> a multiply/accumulate? (percentage wise). > > Probably depends on the chip. The last time I used a floating point dsp > (C30!) all floating point ops (add, sub, mul, mac) finished in a single > cycle. (I think.) > > Ray I entered into the middle of this thread so unless I have the context wrong.... On a SHARC, floating point multiply and floating add have the same cost - one instruction, actually you can do two each in SIMD with some constraints. Fixed point math also operates in one cycle. Instructions on a SHARC operate at the core clock, which can be as high as 450M. They all execute in 1 cycle. I assume that the TI floating point DSPs would be similar. Single cycle (1 instruction) processing is quite normal for DSPs. Algorithms that trade off multiplies for adds are not generally helpful with DSPs. OTOH, these techniques can be very useful for other type of devices such as FPGAs or GP microcontrollers. Al Clark www.danvillesignal.com
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