Fujitsu SPARC VIII-fx HPC-ACE adds instruction prefixes: variablelength instructions for RISC!!!
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From: "Andy "Krazy" Glew" on 24 Dec 2009 16:34 I'm enjoying reading Hot Chips presentations. I'm - happy? chuffed? not surprised? interested? - to see one of the last bastions of RISC fall down. Fujitsu has added an instruction prefix. Albeit a 32 bit instruction prefix, not an 8 bit prefix like the amd x86-64 REX byte. But same idea. New register for the prefix state. Also specifies extended opcodes for new instructions. Pardon the mess, but I'll just cut and paste the text from the slide: Large register sets 2/2 Instruction format for 256 FP registers 8 bit x 4 (3 read +1 write) register number fields are necessary for FMA (Floating-point Multiply and Add) instruction. But SPARC-V9 instruction length is limited (32bits �fixed) Defined a new prefix instruction (SXAR) to specify upper-3bit of register numbers of the following two instructions. SXAR inst1 inst2 Lower-5bit x4 Upper-3bit x4 SXAR (Set XAR) instruction XAR: Extended Arithmetic Register �Set by the SXAR instruction �Valid bit is cleared once the corresponding subsequent instruction gets executed. Operand fields of SXAR fv furd furs1 furs2 furs3 sv surd surs1 surs2 surs3 31 0 fsimd ssimd 16 15 First Upper Register Source-1 bits SXAR1: set XAR for subsequent one instruction. SXAR2: set XAR for subsequent two instructions. |