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From: Walter Roberson on 18 May 2010 00:45 Walter Roberson wrote: > khan Sim wrote: > >> do we define a clock source in simulink model like we define in verilog? >> what is the difference between sample based, time based and frame >> based??? > > http://www.mathworks.com/access/helpdesk/help/toolbox/dspblks/ug/f13-62668.html Sorry for the duplicates; my news server lied to my posting software again and said the message was _not_ posted.
From: khan Sim on 18 May 2010 02:41 Well, i have a confusion, i am getting an input x=[1,512], means number of rows=1 and number of collumns =512 at time 0. t=[0]. the input in data inport would be [t],[x] . now i am getting this data at time 0. it means i am getting data in parallel form. Am i right here??? Is sample based and frame based data acquisition some thing to do with serial or parallel input???? waiting for reply kind regards Khan
From: Sean Little on 18 May 2010 10:24 > fs > for k = 1:512 > if afsb0(k) > amp_max*P_max > fsb0(k) = (amp_max*(P_max^2)./afsb0(k)).*exp(1j*angle(fsb0(k))); > end You are still thinking about this problem in terms of software development. What does a FOR loop mean in terms of hardware? You can solve problems like this using techniques such as "loop unrolling". In other words, you could write a statement for each iteration of the FOR loop, essentially creating 512 parallel copies of the hardware you want. But this can be wasteful of hardware resources on the FPGA, especially since the ANGLE and EXP functions will not be simple to implement. Alternatively, you could increase the clock frequency by a factor of 512 and use a single instance of the hardware. That is the option I would recommend, but this option is more complex, as you will need to design control logic. A simple counter should suffice, but you will need to manually create the upsampling and downsampling logic. I would recommend that you create a simple model that will allow you to debug this process. I have some spline based approximation utilities that I developed for implementing complex functions over known intervals in HDL. I have used this to build an approximation for EXP, and I know this works for other functions also. I will post that material to the file exchange this week. This *might* help you, but if not, you will need to find a way to do the necessary approximations using only HDL supported Simulink blocks or supported EML constructs. I can only advise you in that effort. Sean Little
From: khan Sim on 19 May 2010 06:55 indeed thank you very much for your time, efforts, ideas and guidelines. well i ve seen some demos of hdl , doing fft and stuff. actually they are getting data from signal source with in the model. i want to get the signal from the works space. the signal in workspace is in the form of [1x4] complex data. i ve a confusion, hopefully i think you will remove that. sb is a matrix of [1x4], ie number of rows =1 and number of columns=512 sb is a complex double data, t=[0,1,2,3] i want to input this data to a simulink model. i am using the inport block to input data. i am using the following expression in the data inport in the configuration of simulink model [t;sb]' i wan to store this data in a buffer, and retrieve it later for fft. i am try but not getting any success. thanx
From: khan Sim on 19 May 2010 15:42
well Acting upon your tips, i am starting with a simple model which can do fft for N=8. i getting sample based data from workspace. i want to convert this data from Serial to Parallel. i have used buffer for that with a frame size of 8, but when i run the simulation i get the following error. Error reported by S-function 'sdsprebuff2' in 'basic/Buffer': All sample times for this block must be discrete. No continuous or constant sample times are allowed. Kindly have a look into it anxiously waiting for your reply :) thanx |