Hardware TLB reloaders
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From: Nick Maclaren on 6 Aug 2010 13:20 In article <94ad8368-5fbd-4c8a-a016-492a2a6ab11f(a)f42g2000yqn.googlegroups.com>, MitchAlsup <MitchAlsup(a)aol.com> wrote: > >Do ANY OoO machines with hardware TLB reloaders DRAIN the pipeline to >refill a TLB? I have just had a thought. If I recall, several of the System/370 range used 4-way associativity for TLBs. Now, they weren't out-of- order in the modern sense (though were, in some sense), but that would cause trouble. What do modern hardware reloaders do when they get multiple, CLASHING, TLB uses before the first has completed? That can clearly happen if more memory accesses are allowed than TLB associativity, and possibly in other ways. Or do they ensure that can't happen? Regards, Nick Maclaren.
From: MitchAlsup on 6 Aug 2010 16:50 On Aug 6, 12:20 pm, n...(a)gosset.csi.cam.ac.uk (Nick Maclaren) wrote: > What do modern hardware reloaders do when they get multiple, > CLASHING, TLB uses before the first has completed? That can clearly > happen if more memory accesses are allowed than TLB associativity, > and possibly in other ways. Or do they ensure that can't happen? While I cannot speak for other designers..... This seems to be the kind of problem you simply ignore--to the extent possible. That is, you walk the page tables, install the PTE, and go on with life. If you happen to be walking a set of addresses that will cause thrashing in the PTE, you simpy ignore the problem, install the PTE of the moment and go on with life. In practice, if you have any of these (or have any notion of being hit with one of these), you wil simulate a lot of configurations of the TLB and <hopefully> not observe a severe "fall on the face" problem. If you do observe a problem in TLB performance, you will reconfigure the TLB so as to not have one of these. Hopefully with some analysis of why it happened, and this, then, will drive the reconfiguration. Mitch
From: Robert Myers on 6 Aug 2010 17:43 On Aug 6, 4:50 pm, MitchAlsup <MitchAl...(a)aol.com> wrote: > On Aug 6, 12:20 pm, n...(a)gosset.csi.cam.ac.uk (Nick Maclaren) wrote: > > > What do modern hardware reloaders do when they get multiple, > > CLASHING, TLB uses before the first has completed? That can clearly > > happen if more memory accesses are allowed than TLB associativity, > > and possibly in other ways. Or do they ensure that can't happen? > > While I cannot speak for other designers..... > > This seems to be the kind of problem you simply ignore--to the extent > possible. That is, you walk the page tables, install the PTE, and go > on with life. If you happen to be walking a set of addresses that will > cause thrashing in the PTE, you simpy ignore the problem, install the > PTE of the moment and go on with life. > > In practice, if you have any of these (or have any notion of being hit > with one of these), you wil simulate a lot of configurations of the > TLB and <hopefully> not observe a severe "fall on the face" problem. > If you do observe a problem in TLB performance, you will reconfigure > the TLB so as to not have one of these. Hopefully with some analysis > of why it happened, and this, then, will drive the reconfiguration. > Is it too much of a reach to say that the Halting Theorem has to apply to hardware, too? Robert.
From: Nick Maclaren on 6 Aug 2010 18:02 In article <68e616b4-c45d-4b58-a1ed-9bb08f9ae3c9(a)t20g2000yqa.googlegroups.com>, MitchAlsup <MitchAlsup(a)aol.com> wrote: > >> What do modern hardware reloaders do when they get multiple, >> CLASHING, TLB uses before the first has completed? That can clearly >> happen if more memory accesses are allowed than TLB associativity, >> and possibly in other ways. Or do they ensure that can't happen? > >While I cannot speak for other designers..... > >This seems to be the kind of problem you simply ignore--to the extent >possible. That is, you walk the page tables, install the PTE, and go >on with life. If you happen to be walking a set of addresses that will >cause thrashing in the PTE, you simpy ignore the problem, install the >PTE of the moment and go on with life. I was afraid of that :-( >In practice, if you have any of these (or have any notion of being hit >with one of these), you wil simulate a lot of configurations of the >TLB and <hopefully> not observe a severe "fall on the face" problem. >If you do observe a problem in TLB performance, you will reconfigure >the TLB so as to not have one of these. Hopefully with some analysis >of why it happened, and this, then, will drive the reconfiguration. I have heard of systems that deadlocked, but the only case I have actually seen is when I managed to deadlock an SGI Origin, and that had the extra amusement of cross-board TLB misses .... Regards, Nick Maclaren.
From: Nick Maclaren on 6 Aug 2010 18:06
In article <828dcd6e-6316-44a5-a561-3f04180ea5d2(a)g19g2000yqc.googlegroups.com>, Robert Myers <rbmyersusa(a)gmail.com> wrote: > >Is it too much of a reach to say that the Halting Theorem has to apply >to hardware, too? No. Mathematics is not mocked. I have had far too many managers and other idiots tell me that something mathematically insoluble could be solved by new technology/gimmicks/marketing/bullshit. So far, none have proved their point :-) Regards, Nick Maclaren. |