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From: Laron on 14 Jan 2010 10:30
>On Wed, 13 Jan 2010 02:23:24 -0600, Laron wrote:
>
>> Hi,
>>
>> In CDMA IS-95 standard, we should insert one zero after 14
>> consecutive "0" in I/Q short PN sequence under SR1 with length cycle
>> 2^15,so as to generate "1000..(15 consecutive zeros)".
>> Using LFSR, is there any convenient way to do this?
>
>Define "convenient". All the ways that I can think of devolve to lots of

>extra logic, at least compared to the simple elegance of a LFSR.
>
>* A 14-input OR gate, and a zero stuffer.
>* A counter that's reset by a '1', that forces a bit stuff at value =
14.
>* Just store all 65536 bits in memory and reel them out two-by-two.
> This would use more space than logic in an ASIC or FPGA, but if
> you've got a system that's heavy on memory (like a microprocessor)
> it may be the way to go.
>
>--
>www.wescottdesign.com
>
want to implement in fpga, any other idea?
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