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From: Jerry Avins on 30 Jan 2010 14:14
lakshmi3489 wrote:
> Hi there
> I am going through the data sheet for AD9445. It is configured to be
> used in the LVDS mode. The output signals are as such:
>
> 14 bit data values(D0+,D0-,.........D13+,D13-)
>
> OR- and OR+ (out of range bits)
>
> DCO- and DCO + (Data Clock Output)
>
>
> What does the term "Data Clock output" mean??? is it the conversion
> time the ADC took???
>
> If I were using a buffer and collecting the data values how do I treat
> the OR and DCO bits.
>
>
> Hope someone help me out.

Can't you find reference to it on a timing diagram? It's waveform will
probably make its use clear. Does the AD9445 have a serial output mode?

Jerry
--
Engineering is the art of making what you want from things you can get.
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From: Symon on 1 Feb 2010 05:45
On 1/30/2010 10:19 PM, Tim Wescott wrote:
> Note that if the device provides a DCO you're in a realm where you have
> pay attention to constraints on length-matching all of the signal traces,
> and probably maintaining some semblance of controlled impedance, too.
>
Length-matching, probably not. The ADC is going at 125 MSPS. The signal
goes along the wires at 6 inches/ns or so. That's four feet for a single
cycle. You'd need some crazy layout for length matching to be a problem.
The DCO is to cope with delays in the device, which turn out to be about
3ns or so.

Impedance matching, well, maybe. IIRC some AD devices have awful LVDS
outputs without termination resistors. Yuk.
HTH., Syms.
From: Tim Wescott on 1 Feb 2010 11:14
On Mon, 01 Feb 2010 10:45:20 +0000, Symon wrote:

> On 1/30/2010 10:19 PM, Tim Wescott wrote:
>> Note that if the device provides a DCO you're in a realm where you have
>> pay attention to constraints on length-matching all of the signal
>> traces, and probably maintaining some semblance of controlled
>> impedance, too.
>>
> Length-matching, probably not. The ADC is going at 125 MSPS. The signal
> goes along the wires at 6 inches/ns or so. That's four feet for a single
> cycle. You'd need some crazy layout for length matching to be a problem.
> The DCO is to cope with delays in the device, which turn out to be about
> 3ns or so.

I should have clarified: by "pay attention" I mean to remember the
distance/time relatinship and think how closely the traces need to be
matched. If that distance ends up being three times the circumference of
the proposed board, then you're safe to make a conscious decision to stop
thinking about it.

Of course, a 200 foot long board is a rarity...

--
www.wescottdesign.com
From: lakshmi3489 on 8 Feb 2010 02:24

>Whether the latency concerns you or not depends on what you are doing
>with the data. If you are doing time correlation to another signal or
>need to know the exact capture time for some other reason, then you do
>care about the latency. But for normal radio applications, you don't
>care about any delays in the processing chain. A pipelined ADC
>samples the input on each clock cycle and starts a conversion process
>that consists of a number of steps. Each step is handled by a
>separate piece of hardware inside the ADC. This works like a bucket
>brigade where each person is handling a bucket at any given time so a
>bucket goes into the line at a certain rate and a bucket comes out at
>a certain rate, but any given bucket takes a much longer time to get
>through the whole line. As long as you don't need to be concerned
>with how long a given sample takes to get through the ADC, you just
>consider that a sample comes out of the ADC on each clock cycle.
>
>So do you care if the data is delayed from the analog signal as long
>as you get a sample on each clock?
>
>BTW, I have no idea what a differential input FIFO is. Are you saying
>that the differential inputs on the FPGA can feed a FIFO? Do you
>understand that the differential LVDS inputs are immediately
>translated to single signals on the inside? So D0+ and D0- on the
>outside will just be D0 on the inside. Then you can route them
>anywhere you wish. But I don't see anywhere that you said you are
>using an FPGA, that seems to be the assumption someone else made.
>Maybe you are using a FIFO IC that has differential inputs? Is that
>the case?
>
>Rick
>

Let me clarify:

1. My differential output signals are connected to the pins of my FPGA,

here i collect them using a utility differential signaling buffer which
as you rightly put converts D0+,D0- to Do.

I collect the data using the data clock that I am receiving.

2. Looking at what been been written regarding the latency. I understand
now that i do not need to worry about it, but instead just collect data for
every rising edge of my data clock.


I just want to thank everyone for helping me with this. You guys are
great !!!


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