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From: David Kanter on 4 Feb 2010 02:20
On Feb 3, 9:55 pm, Del Cecchi <delcecchinospamoftheno...(a)gmail.com>
wrote:
> MitchAlsup wrote:
> > On Feb 3, 12:46 pm, "Paul A. Clayton" <paaronclay...(a)embarqmail.com>
> > wrote:
> >> By the way, I get the impression that traditional packaging
> >> does not use thicker connections for power/ground.  If so, why?
>
> > Depends on what you mean. I have seen packages that have power and
> > ground planes with thicker copper layers than the signal layers
> > (sometimes even clocks are routed up here), and I have seen silicon
> > designs where a lot of the upper layer metalization was used for power
> > and grounding (and a few critical signals). On the other hand I have
> > seen the power and ground routes completely intermeshed with the
> > signal layers to provide more localized current returns and treat the
> > adjacent wires more like on-die transmission lines. So you question
> > needs refinement before any reasonable answer can be given.
>
> >> Would the assembly machines be that much more expensive?
>
> > No, but using two different wire sizes would be expensive. However
> > this is mostly moot due to flip packaging being de rigeuer anyway.
>
> >> Or would thicker power/ground connections
> >> be pointless because the limit is not the amount of power
> >> but the distribution of power?
>
> > It's both, in addition as the edge speed gets faster than 300 ps, on-
> > die capacitive decoupling become manditory, so its not the
> > distribution of power that is important, its the distribution of power
> > as seen by 10-60 ps current spikes of the bigger gates in the design.
> > It is simply impossible to decouple these from outside the chip
> > itself. It is difficult to decouple these inside the die, also.
>
> > As to why no through vias--DRAMs use deep vias (trench capacitors),
> > but realistically to get all the way through the wafer would take at
> > least a dozen iterations of spin-on-photo; bake, expose, develope,
> > rinse, etch, wash repeat. If yo mde the vias big enough to fill with
> > metal for power and ground routes, there would have significant
> > inductance, and high yield problems due to step coverage on
> > metalization, groini boundaries, and general control of the metal. If
> > you started with a via "about" the size of a 'pad' and etched a
> > triangular via to the bottom you might be able to get the metalization
> > coverage to deliver power and yield, but at this point you are not
> > smaller than using it from the front.
>
> > I did see a presentation on through silicon vias a decade ago, but the
> > purpose was to use silicon vias to allow individual nerve fibers to
> > reconnect after nerve surgury. Had almost nothing to do with chips as
> > we understand them.
>
> > Mitch
>
> If my memory doesn't deceive me, the upper metal levels of some cmos
> processes had thicker copper as an option.

Yes. Intel uses a huge 19.4um M9 in their 32nm process for their
power gating and distribution. I don't know how big the wires between
the die and package are...but I imagine they are in the same ballpark.

David
From: Kai Harrekilde-Petersen on 4 Feb 2010 16:40
MitchAlsup <MitchAlsup(a)aol.com> writes:

> As to why no through vias--DRAMs use deep vias (trench capacitors),
> but realistically to get all the way through the wafer would take at
> least a dozen iterations of spin-on-photo; bake, expose, develope,
> rinse, etch, wash repeat. If yo mde the vias big enough to fill with
> metal for power and ground routes, there would have significant
> inductance, and high yield problems due to step coverage on
> metalization, groini boundaries, and general control of the metal. If
> you started with a via "about" the size of a 'pad' and etched a
> triangular via to the bottom you might be able to get the metalization
> coverage to deliver power and yield, but at this point you are not
> smaller than using it from the front.

Ah, but you can backlap the wafer to reduce the thickness - the
8-10-12 mil seems to be pretty standard, and I saw a presentation just
the other day of a 15um backlap. They said that at that point, it's
not how to do the backlapping that becomes the problem, it's how to
handle the wafer afterwards :-)

> I did see a presentation on through silicon vias a decade ago, but the
> purpose was to use silicon vias to allow individual nerve fibers to
> reconnect after nerve surgury. Had almost nothing to do with chips as
> we understand them.

Same company was showing off silicon vias. But this was done in order
to reduce the volume (we're talking about minimal mm^3) of a 3-die +
passives hybrid, not for power issues.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
From: "Andy "Krazy" Glew" on 5 Feb 2010 22:15
> Paul A. Clayton
> just a technophile

Let me take this opportunity to apologize to Paul, and anyone else who has tried to post on http://public.comp-arch net

It is not really surprising that the public area has been vandalized. Spammed. Paul's posts are still in the history,
but overwritten. I'll install captchas, etc., but am sure that the spammers will figure out those soon.

From: "Andy "Krazy" Glew" on 5 Feb 2010 22:55
Del Cecchi wrote:
> MitchAlsup wrote:
>> As to why no through vias--DRAMs use deep vias (trench capacitors),
>> but realistically to get all the way through the wafer would take at
>> least a dozen iterations of spin-on-photo; bake, expose, develope,
>> rinse, etch, wash repeat.
>>
>> Mitch

> The big thing about all the fancy through wafer vias and 3d packaging is
> whether or not it produces a benefit that is worth the cost of the
> additional processing.
>
> I bet if you searched the patent database of your choice you would come
> up with a bunch.

Yup.

Not just patents:

Through-Silicon Vias: Ready for Volume Manufacturing?
IDMs, foundries and packaging houses are now developing capabilities for through-silicon vias, but more work needs to be
done to address manufacturing costs.
Peter Singer, Editor-in-Chief -- Semiconductor International, 3/1/2008

http://www.semiconductor.net/article/205121-Through_Silicon_Vias_Ready_for_Volume_Manufacturing_.php

However, some of my informants talk more favorably about lift-off: 3D VLSI achieved not by TSV, but by literally taking
the "skin" off the top of a wafer, and placing it on another chip. Or sticking two wafers or chips face to face, and
then pulling them apart, with all the good stuff on the second water sticking to the first. Multiple times.

Blows my mind.I have trouble imagining good yields, but apparently...

I've been going to a conference where a guy has been reporting on this for a decade or so. Started out as a special,
GaAs or SiGe on top of Si for RF, etc., but approaching mass market over the years.

- - -

Hey, here's a comp-arch topic: "obviously" this greatly increases volumetric density - of devices, wires, heat, and, I
suspect, flaws.

How much more dense?

Do you give up anything in terms of reliability? Maybe not: with multiple layers of metal you have something like a
support scaffold. But heat...

Does the increase in density provide enough redundancy to offset any loss in reliability?

Personally I would bet on DRAM or other memory first. Already being stacked. Unclear if need more than edges... but if
you can increase BW 16X you may be able to reduce power 4X.

What applications (not SW, but systems) would benefit from such increased density? Nanobots sailing through your
bloodstream?

Really wonderful tiny computer/storage systems can be built. In a few years, maybe decades. But I suspect the boxes they
go into will not look like PCs or laptops or even iPod or iPads.

Will they still go into boxes? I suspect yes, although probably "packaged" in blobs of organic gel, e.g. tolerated by
the body.

There may be divergent form factors: boxes surrounded by blobs, VS. planar devices deposited on glass, plastic, or the
surface of your contact lenses.

(Hmm, causes me to wonder how useful ID form factors might be. Good cooling. Connecting the 2D planes & 3D bloboxes?

From: Del Cecchi on 6 Feb 2010 19:19
Andy "Krazy" Glew wrote:

snip
>
>
> However, some of my informants talk more favorably about lift-off: 3D
> VLSI achieved not by TSV, but by literally taking the "skin" off the top
> of a wafer, and placing it on another chip. Or sticking two wafers or
> chips face to face, and then pulling them apart, with all the good stuff
> on the second water sticking to the first. Multiple times.
>
> Blows my mind.I have trouble imagining good yields, but apparently...

Just another thing that the outsider like me would say "that can't
possibly work" like Chem-mechanical polish planarization of insulation
layers. Or exposing 30 nanometer shapes with optical lithography.
>
> I've been going to a conference where a guy has been reporting on this
> for a decade or so. Started out as a special, GaAs or SiGe on top of Si
> for RF, etc., but approaching mass market over the years.
>
> - - -
>
> Hey, here's a comp-arch topic: "obviously" this greatly increases
> volumetric density - of devices, wires, heat, and, I suspect, flaws.
>
> How much more dense?
>
> Do you give up anything in terms of reliability? Maybe not: with
> multiple layers of metal you have something like a support scaffold. But
> heat...
>
> Does the increase in density provide enough redundancy to offset any
> loss in reliability?
>
> Personally I would bet on DRAM or other memory first. Already being
> stacked. Unclear if need more than edges... but if you can increase BW
> 16X you may be able to reduce power 4X.
>
> What applications (not SW, but systems) would benefit from such
> increased density? Nanobots sailing through your bloodstream?
>
> Really wonderful tiny computer/storage systems can be built. In a few
> years, maybe decades. But I suspect the boxes they go into will not look
> like PCs or laptops or even iPod or iPads.
>
> Will they still go into boxes? I suspect yes, although probably
> "packaged" in blobs of organic gel, e.g. tolerated by the body.
>
> There may be divergent form factors: boxes surrounded by blobs, VS.
> planar devices deposited on glass, plastic, or the surface of your
> contact lenses.
>
> (Hmm, causes me to wonder how useful ID form factors might be. Good
> cooling. Connecting the 2D planes & 3D bloboxes?
>
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