Integeration with VHDL
in [TCL]
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From: sri on 24 Dec 2009 23:34 Hey all, I am new to tcl/tk and this forum. I wonder whether can we create a GUI based IP core generator like wizard using tcl/tk that changes the parameters in the VHDL source code. This is to avoid providing source code (VHDL code) to customer.
From: Arndt Roger Schneider on 25 Dec 2009 10:59 sri schrieb: > Hey all, > > I am new to tcl/tk and this forum. I wonder whether can we create a > GUI based IP core generator like wizard using tcl/tk that changes the > parameters in the VHDL source code. This is to avoid providing source > code (VHDL code) to customer. Of course, when it is possible to visualize VHDL (partial or complete) then it is possible to create an interactive drawing of it. You need: a 2D-visualization system like tkpath 0.3 or tkzinc for the graphics. A conceptual model, representing VHDL in Tcl --I would choose tcl 8.6 OO as the foundation of said model. A builder, which generates code from the model. best also an VHDL interpreter, reading the generated code into the model --to use it as a two-way tool. In short you need something like Jeszra. Jeszra contain[ed(s)] a statechart designer, which presents states as object-like entities, organized in a hierarchy of states. The visual representation is done through tkzinc --For lack of time, I had to remove the statechart designer from the first public appearance of Jeszra, sorry. -roger
From: sri on 28 Dec 2009 04:53 Hi, Thank you very much for your reply. As I said, I am very new to tcl. So all these terms let me to look for an alternative method, Because it looks like I have to read so many languages > You need: > a 2D-visualization system > like tkpath 0.3 or tkzinc for the > graphics. > > A conceptual model, representing > VHDL in Tcl --I would choose tcl 8.6 OO > as the foundation of said model. > > A builder, which generates code from > the model. > > best also an VHDL interpreter, reading > the generated code into the model > --to use it as a two-way tool. Or can you please elaborate the details. On Dec 25, 8:59 pm, Arndt Roger Schneider <roger.schnei...(a)addcom.de> wrote: > sri schrieb: > > > Hey all, > > > I am new to tcl/tk and this forum. I wonder whether can we create a > > GUI based IP core generator like wizard using tcl/tk that changes the > > parameters in the VHDL source code. This is to avoid providing source > > code (VHDL code) to customer. > > Of course, when it is possible to > visualize VHDL (partial or complete) > then it is possible to create an interactive > drawing of it. > > You need: > a 2D-visualization system > like tkpath 0.3 or tkzinc for the > graphics. > > A conceptual model, representing > VHDL in Tcl --I would choose tcl 8.6 OO > as the foundation of said model. > > A builder, which generates code from > the model. > > best also an VHDL interpreter, reading > the generated code into the model > --to use it as a two-way tool. > > In short you need something like Jeszra. > > Jeszra contain[ed(s)] a statechart designer, which > presents states as object-like entities, > organized in a hierarchy of states. The visual > representation is done through tkzinc > --For lack of time, I had to remove the > statechart designer from the first public > appearance of Jeszra, sorry. > > -roger
From: Arndt Roger Schneider on 28 Dec 2009 06:35 sri schrieb: > Hi, > Thank you very much for your reply. > As I said, I am very new to tcl. So all these terms let me to look for > an alternative method, Because it looks like I have to read so many > languages > > >>You need: >>a 2D-visualization system >>like tkpath 0.3 or tkzinc for the >>graphics. >> >>A conceptual model, representing >>VHDL in Tcl --I would choose tcl 8.6 OO >>as the foundation of said model. >> >>A builder, which generates code from >>the model. >> >>best also an VHDL interpreter, reading >>the generated code into the model >>--to use it as a two-way tool. > > > Or can you please elaborate the details. _Don't ask such balant questions, I don't want to write lengthly essays._ Well, you need to know VHDL, but you don't need to know Tcl for developing either the visual representation nor for the (Tcl-implemented) model. If you want to visualize something, you need to find the "nouns". The nouns are the depictable language-things. With VHDL you can resort to existing logic diagramms and reuse as much as possible from there. The difficult parts are "verbs" --functional elements such as loops. You can either invent some sort of a new verb-noun for such an vhdl language artefact or represent them as interactions between multiple nouns. Start with paper and pencile to design these elements. When you have the nouns (visualized) you also know what properties these elements have and which actions from other nouns are permittable on this noun-- in short the interface. You also know the kindship of your nouns. This you can ouline with paper and pencil, too. Then you have the visual representation and the the "model". Now, you can start to craft the visual artifacts in a 2D-visualization system (or in every illustration programm). After this implement the nouns (model) in Tcl (OO or whatever else suites your problem best). VHDL Generation: The builder (builder is a pattern) is part Tcl and part vhdl. The parser (Tcl) iterates over your model and intiates a compositing in Tcl for vhdl --the composite is mainly vhdl fragments. VHDL Interpretation: Is again a builder, which parses vhdl and generates your model in Tcl from vhdl. I would always implement this part through a fullfledged builder: Parsing vhdl, generating Tcl-code, instantiating the model. To allow code-reviewing for this part, too. -roger [snip]
From: Jonathan Bromley on 28 Dec 2009 15:47
On Thu, 24 Dec 2009 20:34:54 -0800 (PST), sri wrote: > I am new to tcl/tk and this forum. I wonder whether can we create a >GUI based IP core generator like wizard using tcl/tk that changes the >parameters in the VHDL source code. This is to avoid providing source >code (VHDL code) to customer. You mean, something like Xilinx Coregen or Altera MegaWizard? I should imagine it would not be too hard, if your ambitions are limited to working with a single design or family of designs. The other replies you got were, I think, assuming that you wanted to use Tcl to process and visualize VHDL code. Instead, I suspect, you want a user to be able to see a simple block diagram of a design, and configure it by enabling or disabling various input/output ports, tweaking parameters and so on. This you can do (easily, but probably with quite a lot of code and a lot of attention to detail) using Tk's canvas. Then, when the user is happy with their configuration, your GUI should spit out a plain-text file containing some VHDL code - but the code will presumably be fairly simple stuff, just a template with some connections present or missing and some generics set to user-controlled values. Of course, the full generality of the big-name tools would be a major project; but I'm guessing you need to offer your users a configuration tool for one specific piece of IP, or perhaps for a fairly small number of different IP blocks. In such a case, you can probably tolerate the overhead of rewriting the GUI code for each new IP block. Please excuse me if I've misunderstood your intent. -- Jonathan Bromley |