Interesting presentation
|
Prev: Multi-core lag for Left 4 Dead 1 and 2 and Quake 4 on AMD X23800+ processor... why ?
Next: Which is the most beautiful and memorable hardware structure in a CPU?
From: nmm1 on 2 Apr 2010 11:39 In article <693h87-kn7.ln1(a)ntp.tmsw.no>, Terje Mathisen <terje.mathisen(a)tmsw.no> wrote: >Morten Reistad wrote: >> Now, can we attack this from a simpler perspective; can we make >> the L2-memory interaction more intelligent? Like actually make >> a paging system for it? Paging revolutionised the disk-memory >> systems, remember? > >Morten, I've been preaching these equivalences for more than 5 years: > >Old Mainframe: cpu register -> memory -> disk -> tape >Modern micro: cpu register -> cache -> ram -> disk Definitely more than 5 years. My recollection is that you have been doing so for about as long as I have, and we weren't among the first people to say that. Regards, Nick Maclaren.
From: nmm1 on 2 Apr 2010 12:30 In article <hp5254$r1m$1(a)news.eternal-september.org>, Stephen Fuld <SFuld(a)Alumni.cmu.edu.invalid> wrote: >On 4/2/2010 5:07 AM, Terje Mathisen wrote: >> >>> Now, can we attack this from a simpler perspective; can we make >>> the L2-memory interaction more intelligent? Like actually make >>> a paging system for it? Paging revolutionised the disk-memory >>> systems, remember? >> >> Morten, I've been preaching these equivalences for more than 5 years: >> >> Old Mainframe: cpu register -> memory -> disk -> tape >> Modern micro: cpu register -> cache -> ram -> disk > >While this is all, at least sort of, true, the question is what do you >want to do about it. ISTM that the salient characteristics paging, i.e. >memory to disk, interface are that it requires OS interaction in order >to optimize, that the memory to disk interfaces have been getting >narrower (i.e. SATA, Fibre Channel and serial SCSI) not wider, and that >the CPU doesn't directly address the disk. Do you want to narrow the >CPU's addressing range to just include the cache? Do you want the >software to get involved in cache miss processing? > >This is all to say that, as usual, the devil is in the details. :-( Well, yes, but we COULD start by learning from the past! Radical, I know, but I am radical. Simple changes that would help a lot would be to abolish paging, and make all segments (Unix-style, not 8086-style) swappable only, and to have some software control over the amount of cache used (and its algorithms), at least for the higher caches. After all, both techniques worked on the old mainframes (mutis mutandis). Regards, Nick Maclaren.
From: Morten Reistad on 2 Apr 2010 13:57 In article <81l7otF4ipU1(a)mid.individual.net>, Del Cecchi` <delcecchi(a)gmail.com> wrote: >MitchAlsup wrote: >> On Apr 1, 5:40 pm, timcaff...(a)aol.com (Tim McCaffrey) wrote: >> >>>The PCIe 2.0 links on the Clarkdale chips runs at 5G. >> >> >> Any how many dozen meters can these wires run? >> >> Mitch > >Maybe 1 dozen meters, depending on thickness of wire. Wire thickness >depends on how many you want to be able to put in a cable, and if you >want to be able to bend those cables. > >10GbaseT or whatever it is called gets 10 gbits/second over 4 twisted >pairs for 100 meters by what I classify as unnatural acts torturing the >bits. The block codes and stuff involved also add a fair amount of >latency, and considerable power is consumed. If you go for real single mode transceivers with decent ("LX") lasers the distance can be up to 70 kilometers before requiring regeneration. With SFP interfaces you can plug and choose transceivers to your hearts content. At 10G you probably want to use fiber in such a setup to bring down signal processing latencies. Let there be Light! -- mrr
From: Robert Myers on 2 Apr 2010 14:10 On Apr 2, 11:23 am, Stephen Fuld <SF...(a)alumni.cmu.edu.invalid> wrote: > While this is all, at least sort of, true, the question is what do you > want to do about it. ISTM that the salient characteristics paging, i.e.. > memory to disk, interface are that it requires OS interaction in order > to optimize, that the memory to disk interfaces have been getting > narrower (i.e. SATA, Fibre Channel and serial SCSI) not wider, and that > the CPU doesn't directly address the disk. Do you want to narrow the > CPU's addressing range to just include the cache? Do you want the > software to get involved in cache miss processing? > > This is all to say that, as usual, the devil is in the details. :-( On die memory isn't yet big enough to be fussing the details, although I assume we will get there. The better model to look at might be graphics cards that carry a large enough amount of super-fast memory to be interesting as a model for general computation. Robert.
From: Morten Reistad on 2 Apr 2010 22:45
In article <tpqar5pfc05ajvn3329an6v9tcodh58i65(a)4ax.com>, Muzaffer Kal <kal(a)dspia.com> wrote: >On Thu, 01 Apr 2010 22:48:47 -0500, Del Cecchi` <delcecchi(a)gmail.com> >wrote: > >>MitchAlsup wrote: >>> On Apr 1, 5:40 pm, timcaff...(a)aol.com (Tim McCaffrey) wrote: >>> >>>>The PCIe 2.0 links on the Clarkdale chips runs at 5G. >>> >>> >>> Any how many dozen meters can these wires run? >>> >>> Mitch >> >>Maybe 1 dozen meters, depending on thickness of wire. Wire thickness >>depends on how many you want to be able to put in a cable, and if you >>want to be able to bend those cables. >> >>10GbaseT or whatever it is called gets 10 gbits/second over 4 twisted >>pairs for 100 meters by what I classify as unnatural acts torturing the >>bits. > >You should also add to it that this is full-duplex ie simultaneous >transmission of 10G in both directions. One needs 4 equalizers, 4 echo >cancellers, 12 NEXT and 12 FEXT cancellers in addition to a fully >parallel LDPC decoder (don't even talk about the insane requirement on >the clock recovery block). Over the last 5 years probably US$ 100M of >VC money got spent to develop 10GBT PHYs with several startups >disappearing with not much to show for. Torturing the bits indeed (not >the mention torture of the engineers trying to make this thing work.) >-- >Muzaffer Kal Except for the optics, fiber equipment is a lot simpler. Or you can use the SFP interface, and plug in hardware drivers for the media in question. And 10G ethernet is reasonably easily switched over longer distances. Fiber hops can be 70km between amplification, and 400 km between full regeneration. It is fully possible to build a planet-wide 10G switched ethernet. But then the latency would be a problem again. -- mrr |