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From: Dravid on 5 Feb 2010 05:10
Hi all,
Am using lpc2478 for 6.5 TFT LCD development in that am using
256Mb(K4S561632E-FROM SAMSUNG) SDRAM for LCD FRAME BUFFER. can anyone help
me to solve the sdram initialization problem,
i have attached the sdram init coding can anyone suggest me to solve the
sdram initalizing problem.


void sdramInit(void)
{
volatile unsigned short i,dummy;
PINSEL5 &= 0XF0FCFCC0;
PINSEL5 |= 0X05010115;
PINMODE5 &= 0xF0FCFCC0;
PINMODE5 |= 0x0A02022A;
PINSEL6 |= 0X55555555;
PINMODE6 |= 0XAAAAAAAA;
PINSEL8 &= 0XC0000000;
PINSEL8 |= 0X15555555;
PINMODE8 &= 0XC0000000;
PINMODE8 |= 0X2AAAAAAA;
PCONP |=0X800;
EMC_CTRL =1;
EMC_DYN_RD_CFG =1;
EMC_DYN_RASCAS0 |=0X00000303;
EMC_DYN_RP = 2;
EMC_DYN_RAS = 3;
EMC_DYN_SREX= 1;
EMC_DYN_APR = 2;
EMC_DYN_DAL = 3;
EMC_DYN_WR = 2;
EMC_DYN_RC = 3;
EMC_DYN_RFC = 3;
EMC_DYN_XSR = 7;
EMC_DYN_RRD = 1;
EMC_DYN_MRD = 1;
EMC_DYN_CFG0= 0X00000680;
EMC_DYN_CTRL= 0X183; //Issue SDRAM NOP (no operation) command ;
for(i=0; i<0x40; i++)
{
__asm
{
NOP
}
}
mdelay(200);
EMC_DYN_CTRL|=0x103; // Issue SDRAM PALL (precharge all) command.
EMC_DYN_RFSH = 0X2;
for(i= 128; i; --i); // > 128 clk
EMC_DYN_RFSH = 0x1c;
EMC_DYN_CTRL|=0x83;
//Issue SDRAM MODE command.
dummy = *((volatile unsigned short*)(LCD_FRAME_BUFFER | (22 << 11 )));
EMC_DYN_CTRL = 0x3; //Issue SDRAM norm command ;
EMC_DYN_CFG0|=0x80000; //Buffer enabled for accesses to DCS0 chip
}


Regards,
Dravid.

---------------------------------------
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From: Boudewijn Dijkstra on 5 Feb 2010 13:30
Op Fri, 05 Feb 2010 11:10:54 +0100 schreef Dravid
<dravidv(a)n_o_s_p_a_m.gmail.com>:
> Hi all,
> Am using lpc2478 for 6.5 TFT LCD development in that am using
> 256Mb(K4S561632E-FROM SAMSUNG) SDRAM for LCD FRAME BUFFER. can anyone
> help
> me to solve the sdram initialization problem,
> i have attached the sdram init coding can anyone suggest me to solve the
> sdram initalizing problem.

http://catb.org/~esr/faqs/smart-questions.html


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From: Sergey Volodin on 13 Feb 2010 04:19
> help
> me to solve the sdram initialization problem

I use both SRAM and SDRAM.
It works with next initialization proc.(RowleyCW)
/
******************************************************************************
** Function name: ConfigureEMC
**
** Descriptions: Configure EMC for external SDRAM, NAND and NOR FLASH
** parameters: None
** Returned value: None
**
******************************************************************************/
static void ConfigureEMC(void)
{
volatile unsigned int i, dummy = dummy;

EMC_CTRL = 0x00000001;
PCONP |= 0x00000800; /* Turn on EMC PCLK */
PINSEL4 = 0x50000000;
#ifdef USE_32_BIT_DATABUS
PINSEL5 = 0x55010115;
PINSEL7 = 0x55555555;
#else
PINSEL5 = 0x05050555;
#endif
PINSEL6 = 0x55555555;
PINSEL8 = 0x55555555;
PINSEL9 = 0x50555555;

//all registers...
#ifdef USE_32_BIT_DATABUS
EMC_DYN_RP = 1; //>20ns = 2 clk
EMC_DYN_RAS = 3; //>45ns = 3 clk
EMC_DYN_SREX = 5; //>80-100ns = 6 clk
EMC_DYN_APR = 1; //
EMC_DYN_DAL = 5; //2 clk
EMC_DYN_WR = 1; //2 clk
EMC_DYN_RC = 5; //>65ns = 4 clk
EMC_DYN_RFC = 5; //>80-100ns = 6 clk
EMC_DYN_XSR = 5; //>80-100ns = 6 clk
EMC_DYN_RRD = 1; //>15ns = 1-2 clk
EMC_DYN_MRD = 1; //2 clk
EMC_DYN_RD_CFG = 1; //or 1,2,3

EMC_DYN_RASCAS0 = 0x00000202;
EMC_DYN_CFG0 = 0x00005480;
#else
EMC_DYN_RP = 2; //>20ns = 2 clk
EMC_DYN_RAS = 3; //>45ns = 3 clk
EMC_DYN_SREX = 7; //>80-100ns = 6 clk
EMC_DYN_APR = 2; //
EMC_DYN_DAL = 5; //2 clk
EMC_DYN_WR = 1; //2 clk
EMC_DYN_RC = 5; //>65ns = 4 clk
EMC_DYN_RFC = 5; //>80-100ns = 6 clk
EMC_DYN_XSR = 7; //>80-100ns = 6 clk
EMC_DYN_RRD = 1; //>15ns = 1-2 clk
EMC_DYN_MRD = 2; //2 clk
EMC_DYN_RD_CFG = 1; //or 1,2,3

EMC_DYN_RASCAS0 = 0x00000303;
EMC_DYN_CFG0 = 0x00000680;
#endif

delayMs(100); //wait 100mS

EMC_DYN_CTRL = 0x00000183; //Send command: NOP

delayMs(200); //wait 200mS

//Send command: PRECHARGE-ALL, shortest possible refresh period
EMC_DYN_CTRL = 0x00000103;
EMC_DYN_RFSH = 0x00000002;

//wait 128 ABH clock cycles
for(i=0; i<0x40; i++) asm volatile(" nop");

//Set correct refresh period
EMC_DYN_RFSH = 28;

//Send command: MODE
EMC_DYN_CTRL = 0x00000083;

//Set mode register in SDRAM
#ifdef USE_32_BIT_DATABUS
dummy = *((volatile unsigned int*)(SDRAM_BASE_ADDR | (0x22 << 11)));
#else
dummy = *((volatile unsigned int*)(SDRAM_BASE_ADDR | (0x33 << 12)));
#endif

//Send command: NORMAL
EMC_DYN_CTRL = 0x00000000;

//Enable buffer
EMC_DYN_CFG0 |= 0x00080000;

//initial system delay
delayMs(1);

EMC_STA_WAITWEN0 = 0x2;
EMC_STA_WAITOEN0 = 0x2;
EMC_STA_WAITRD0 = 0x1f;
EMC_STA_WAITPAGE0 = 0x1f;
EMC_STA_WAITWR0 = 0x1f;
EMC_STA_WAITTURN0 = 0xf;
EMC_STA_CFG0 = 0x00000081;

EMC_STA_WAITWEN1 = 0x2;
EMC_STA_WAITOEN1 = 0x2;
EMC_STA_WAITRD1 = 0x8;
EMC_STA_WAITPAGE1 = 0x1f;
EMC_STA_WAITWR1 = 0x8;
EMC_STA_WAITTURN1 = 0xf;
EMC_STA_CFG1 = 0x00000080;

}

Regards
Sergey

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