LVPECL to PECL to LVPECL
in [Design]
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From: Rene Tschaggelar on 16 May 2010 09:00 The supply variety on ECL parts in general has ever been diminishing over the years, the variety is not even continuous. I should now connect an FPGA to a bunch of ECLs. The LVDS to LVPECL translation can be done with a 65LVDS100. Further I can only find a few ECL parts and finally I should connect to LVPECL again. I consider now lowering the Vcc for the PECL to 3.3V and set the associated GND to -1.9V for a blunt signal connection. The signals of (LV)ECL in general are referenced to the respective Vcc, so this should be doable. FPGA-LVDS -> 65LVDS100(3.3V,0V) -> PECL (+3.3V,-1.9V) -> LVPECL(3.3V,0V) Differential signal may have less problems than single ended in this configuration, I guess. A one point I'll have to go single ended though. Rene
From: Andrew Holme on 16 May 2010 11:58 "Rene Tschaggelar" <none(a)none.net> wrote in message news:j0SHn.4900$yx.1201(a)newsfe13.iad... > The supply variety on ECL parts in general has ever > been diminishing over the years, the variety is not > even continuous. I should now connect an FPGA to a > bunch of ECLs. The LVDS to LVPECL translation can be > done with a 65LVDS100. Further I can only find a few > ECL parts and finally I should connect to LVPECL > again. I consider now lowering the Vcc for the PECL > to 3.3V and set the associated GND to -1.9V for a blunt > signal connection. The signals of (LV)ECL in general > are referenced to the respective Vcc, so this should > be doable. > > FPGA-LVDS -> 65LVDS100(3.3V,0V) -> PECL (+3.3V,-1.9V) -> LVPECL(3.3V,0V) > > Differential signal may have less problems than single > ended in this configuration, I guess. A one point I'll > have to go single ended though. > > > Rene MAX9375 is another option for LVDS to LVPECL
From: John Larkin on 16 May 2010 12:05 On Sun, 16 May 2010 15:00:22 +0200, Rene Tschaggelar <none(a)none.net> wrote: >The supply variety on ECL parts in general has ever >been diminishing over the years, the variety is not >even continuous. I should now connect an FPGA to a >bunch of ECLs. The LVDS to LVPECL translation can be >done with a 65LVDS100. Further I can only find a few >ECL parts and finally I should connect to LVPECL >again. I consider now lowering the Vcc for the PECL >to 3.3V and set the associated GND to -1.9V for a blunt >signal connection. The signals of (LV)ECL in general >are referenced to the respective Vcc, so this should >be doable. > >FPGA-LVDS -> 65LVDS100(3.3V,0V) -> PECL (+3.3V,-1.9V) -> LVPECL(3.3V,0V) > >Differential signal may have less problems than single >ended in this configuration, I guess. A one point I'll >have to go single ended though. > > >Rene Differential connections between an FPGA and PECL can usually be done directly. Some FPGAs will make legit LVPECL, allowing all chips to run off 3.3 and ground (well, if the ECL is willing, like the EL and EP parts.) If the FPGA makes LVDS output levels, the common-mode will be a little low for safety, so the ecl Vee should be -1 or. FPGA LVDS (3.3/gnd) to pecl 3.3/-1.9) should work fine. Every LVDS receiver that I've tested, discrete and inside Xilinx, behaved like a pretty good rail-to-rail comparator. So LVDS receivers are usually happy looking at differential PECL, or single-ended PECL if you hook the other input to Vbb. Single-ended 3.3 volt CMOS will drive PECL. A few older ECL parts don't like being pulled all the way up to Vcc, but most new stuff is OK. ONsemi, Arizona Microtech, and Micrel still make ECL. John
From: Robert Baer on 17 May 2010 03:41 Andrew Holme wrote: > "Rene Tschaggelar" <none(a)none.net> wrote in message > news:j0SHn.4900$yx.1201(a)newsfe13.iad... >> The supply variety on ECL parts in general has ever >> been diminishing over the years, the variety is not >> even continuous. I should now connect an FPGA to a >> bunch of ECLs. The LVDS to LVPECL translation can be >> done with a 65LVDS100. Further I can only find a few >> ECL parts and finally I should connect to LVPECL >> again. I consider now lowering the Vcc for the PECL >> to 3.3V and set the associated GND to -1.9V for a blunt >> signal connection. The signals of (LV)ECL in general >> are referenced to the respective Vcc, so this should >> be doable. >> >> FPGA-LVDS -> 65LVDS100(3.3V,0V) -> PECL (+3.3V,-1.9V) -> LVPECL(3.3V,0V) >> >> Differential signal may have less problems than single >> ended in this configuration, I guess. A one point I'll >> have to go single ended though. >> >> >> Rene > > MAX9375 is another option for LVDS to LVPECL > > Except that they are one of the infinite number of Maxim parts that are not made..
From: Andrew Holme on 18 May 2010 13:32
"Robert Baer" <robertbaer(a)localnet.com> wrote in message news:t8-dnaB5N5i8bm3WnZ2dnUVZ_oOdnZ2d(a)posted.localnet... > Andrew Holme wrote: >> "Rene Tschaggelar" <none(a)none.net> wrote in message >> news:j0SHn.4900$yx.1201(a)newsfe13.iad... >>> The supply variety on ECL parts in general has ever >>> been diminishing over the years, the variety is not >>> even continuous. I should now connect an FPGA to a >>> bunch of ECLs. The LVDS to LVPECL translation can be >>> done with a 65LVDS100. Further I can only find a few >>> ECL parts and finally I should connect to LVPECL >>> again. I consider now lowering the Vcc for the PECL >>> to 3.3V and set the associated GND to -1.9V for a blunt >>> signal connection. The signals of (LV)ECL in general >>> are referenced to the respective Vcc, so this should >>> be doable. >>> >>> FPGA-LVDS -> 65LVDS100(3.3V,0V) -> PECL (+3.3V,-1.9V) -> LVPECL(3.3V,0V) >>> >>> Differential signal may have less problems than single >>> ended in this configuration, I guess. A one point I'll >>> have to go single ended though. >>> >>> >>> Rene >> >> MAX9375 is another option for LVDS to LVPECL > Except that they are one of the infinite number of Maxim parts that are > not made.. Not made in quantity, discontinued or not easy to buy through distribution? I got samples from Maxim quite recently. |