MTD: Fix Orion NAND driver compilation with ARM OABI
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From: Nicolas Pitre on 23 Apr 2010 14:00 On Fri, 23 Apr 2010, Artem Bityutskiy wrote: > On Fri, 2010-04-23 at 08:54 -0400, Nicolas Pitre wrote: > > On Fri, 23 Apr 2010, Artem Bityutskiy wrote: > > > > > On Wed, 2010-03-31 at 15:01 +0300, Paulius Zaleckas wrote: > > > > On 03/25/2010 06:26 PM, Nicolas Pitre wrote: > > > > > On Thu, 25 Mar 2010, Paulius Zaleckas wrote: > > > > > > > > > >> We must tell GCC to use even register for variable passed > > > > >> to ldrd instruction. Without this patch GCC 4.2.1 puts this > > > > >> variable to r2/r3 on EABI and r3/r4 on OABI, so force it to > > > > >> r2/r3. This does not change anything when EABI and OABI > > > > >> compilation works OK. > > > > >> > > > > >> Without this patch and with OABI I get: > > > > >> CC drivers/mtd/nand/orion_nand.o > > > > >> /tmp/ccMkwOCs.s: Assembler messages: > > > > >> /tmp/ccMkwOCs.s:63: Error: first destination register must be even -- `ldrd r3,[ip]' > > > > >> make[5]: *** [drivers/mtd/nand/orion_nand.o] Error 1 > > > > >> > > > > >> Signed-off-by: Paulius Zaleckas<paulius.zaleckas(a)gmail.com> > > > > > > > > > > Acked-by: Nicolas Pitre<nico(a)fluxnic.net> > > > > > > > > David, > > > > > > > > Will you take this patch? > > > > Or you are waiting till I will add all Cc as Jamie suggested? > > > > > > Meanwhile, I've pushed your patch to my l2-mtd-2.6.git / dunno. > > > > I think it should go to mainline. It is not perfect, but still better > > than the current situation. > > Fine with me, but not up to me. But I guess Andrew could merge it. The patch is providing a fix to my own code, and I acked it already. The root of the problem is a defficiency in gcc, and dwmw2 asked that a PR be filled for that and a reference to it added to the patch. This has been done. Nicolas -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Andrew Morton on 23 Apr 2010 14:10 On Fri, 23 Apr 2010 13:50:10 -0400 (EDT) Nicolas Pitre <nico(a)fluxnic.net> wrote: > > Fine with me, but not up to me. But I guess Andrew could merge it. > > The patch is providing a fix to my own code, and I acked it already. The > root of the problem is a defficiency in gcc, and dwmw2 asked that a PR > be filled for that and a reference to it added to the patch. This has > been done. Well, I merged it and can send it upstream. But Jamie's observations give me pause? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Nicolas Pitre on 23 Apr 2010 14:30 On Fri, 23 Apr 2010, Andrew Morton wrote: > On Fri, 23 Apr 2010 13:50:10 -0400 (EDT) > Nicolas Pitre <nico(a)fluxnic.net> wrote: > > > > Fine with me, but not up to me. But I guess Andrew could merge it. > > > > The patch is providing a fix to my own code, and I acked it already. The > > root of the problem is a defficiency in gcc, and dwmw2 asked that a PR > > be filled for that and a reference to it added to the patch. This has > > been done. > > Well, I merged it and can send it upstream. But Jamie's observations > give me pause? What observation? Let me find that. Nicolas -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Nicolas Pitre on 23 Apr 2010 15:10 On Thu, 25 Mar 2010, Jamie Lokier wrote: > Paulius Zaleckas wrote: > > Signed-off-by: Paulius Zaleckas <paulius.zaleckas(a)gmail.com> > > It's probably worth including the people who weighed in on the > discussion with 'Cc:' headers. > > > - uint64_t x; > > + /* > > + * Since GCC has no proper constraint (PR 43518) > > + * force x variable to r2/r3 registers as ldrd instruction > > + * requires first register to be even. > > + */ > > + register uint64_t x asm ("r2"); > > + > > asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); > > buf64[i++] = x; > > The "register...asm" looks fine, but it occurs to me the constraints > are too weak (and they were before), so GCC could optimise that to the > wrong behaviour. > > The "volatile" prevents GCC deleting the asm if it's output isn't > used, but it doesn't stop GCC from reordering the asms, for example if > it decides to unroll the loop. It probably won't reorder in that > case, but it could. The result would be out of order values stored > into buf[]. It could even move the ldrd earlier than the prior byte > accesses, or after the later byte accesses. I don't see how that could happen. The store into buf[] puts a dependency on the output constraint of the inline asm statement. And by vertue of being volatile, gcc cannot cache the result of the output from the asm as if it was a pure function. > Any one of these should fix it: > > - Make io_base a pointer-to-volatile-u64 or cast it in the asm, and > make sure to dereference it and use an "m" constraint (or > tighter, such as "Q", if ldrd needs it). It must be u64, not > pointer-to-void, to tell GCC the size. That tells GCC which memory > the asm accesses, and the volatile dereference should tell GCC > not to reorder them in principle (but the GCC manual doesn't > make a specific promise about this for asms). The LDRD has special range constraints on its addressing mode which is not expressable with any of the available gcc memory constraints. > You aren't supposed to dereference pointers used with read{b,w,l} > anyway. It doesn't matter in this driver because we "know" it's only > used on an SoC where read{b,w,l} don't do any address translation. > But will that always be true? I suppose the cleanest approach is to > define readq, the 64-bit analogue of readl, and use that here. x86 > already defines readq, so it's got precedent. But yet it is not all ARM variants that can do 64-bit accesses. Anything pre ARMv5 doesn't have the LDRD instruction, and the equivalent LDM is not a possible substitute with regard to memory bus access either. So I'd prefer to keep it as an obvious local exception that happens to exploit some specifics of the actual hardware implementation rather than something that was architecturally defined. Nicolas -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Jamie Lokier on 23 Apr 2010 23:00
Nicolas Pitre wrote: > On Thu, 25 Mar 2010, Jamie Lokier wrote: > > > asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); > > > buf64[i++] = x; > > > > The "register...asm" looks fine, but it occurs to me the constraints > > are too weak (and they were before), so GCC could optimise that to the > > wrong behaviour. > > > > The "volatile" prevents GCC deleting the asm if it's output isn't > > used, but it doesn't stop GCC from reordering the asms, for example if > > it decides to unroll the loop. It probably won't reorder in that > > case, but it could. The result would be out of order values stored > > into buf[]. It could even move the ldrd earlier than the prior byte > > accesses, or after the later byte accesses. > > I don't see how that could happen. The store into buf[] puts a > dependency on the output constraint of the inline asm statement. And by > vertue of being volatile, gcc cannot cache the result of the output from > the asm as if it was a pure function. The store into buf[] dependency doesn't stop this, after unrolling: asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); buf64[i++] = x; asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); buf64[i++] = x; from being reordered as this asm volatile ("ldrd\t%0, [%1]" : "=&r" (x2) : "r" (io_base)); asm volatile ("ldrd\t%0, [%1]" : "=&r" (x1) : "r" (io_base)); buf64[i++] = x1; buf64[i++] = x2; because the asm doesn't depend on memory, just register inputs and outputs; I'm not sure what you mean about the volatile stopping gcc from treating the asm as a pure function. Is that meaning of volatile in the asm documentation? (volatile on asm doesn't mean the same as volatile on a function, or volatile on a pointer). > > Any one of these should fix it: > > > > - Make io_base a pointer-to-volatile-u64 or cast it in the asm, and > > make sure to dereference it and use an "m" constraint (or > > tighter, such as "Q", if ldrd needs it). It must be u64, not > > pointer-to-void, to tell GCC the size. That tells GCC which memory > > the asm accesses, and the volatile dereference should tell GCC > > not to reorder them in principle (but the GCC manual doesn't > > make a specific promise about this for asms). > > The LDRD has special range constraints on its addressing mode which is > not expressable with any of the available gcc memory constraints. 'Q' A memory reference where the exact address is in a single register (''m'' is preferable for 'asm' statements) If 'r' is good enough for io_base, 'Q' should be good enough for *io_base. -- Jamie -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ |