Prev: superscalar and superpipelined
Next: VLIW pre-history
From: SANJEEV KUMAR DHABRE on 27 Apr 2007 13:45
Hello,
I am a Master's student of Dept of Computer Science, IIT Madras,
India.
I have visited your web site that contains documentation of UP3 board
and it is very detailed. I am working on multiple clock domains and I
have a UP3 kit. Do you have any sample multiple clock domain design
that you implemented on UP3 board with pin assignments? If so, could
you please provide relevant design files and the project files?
Thanking you
Sanjeev Dhabre

 | 
Pages: 1
Prev: superscalar and superpipelined
Next: VLIW pre-history