Nested interrupt
in [Embedded]
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From: thiru_vid on 5 Dec 2009 10:08 Timer1 ISR _______________________________________________________________ | | | |___________ <----Do some calculation it takes around 8us with in timer 1--> <--------- Each and every 10us, the timer 1 ISR is executed -----------> Timer 3 ISR _________ _________ ________ _________ ________ | | | | | | | | | | |_____| |_____| |______| |_____| | <---1.5---> <-----2us-------> I am using TMS320F2812 microcontroller. i need to implement the timer 3 ISR are executed within Timer 1 ISR. Is it possible to implement the same? Any one can you please help me for that. --------------------------------------- This message was sent using the comp.arch.embedded web interface on http://www.EmbeddedRelated.com
From: Rich Webb on 5 Dec 2009 12:13 On Sat, 05 Dec 2009 09:08:50 -0600, "thiru_vid" <thiru_vid(a)yahoo.co.in> wrote: >Timer1 ISR > _______________________________________________________________ >| | >| |___________ ><----Do some calculation it takes around 8us with in timer 1--> ><--------- Each and every 10us, the timer 1 ISR is executed >-----------> > > > >Timer 3 ISR > _________ _________ ________ _________ ________ >| | | | | | | | | | |_____| |_____| >|______| |_____| | ><---1.5---> ><-----2us-------> > >I am using TMS320F2812 microcontroller. >i need to implement the timer 3 ISR are executed within Timer 1 ISR. Is it >possible to implement the same? >Any one can you please help me for that. A dual core? An FPGA? Otherwise, as described, I don't see it as possible. If Timer3 preempts Timer1, leaving 0.5 usec out of every 2.0 usec available for Timer1 (not counting overhead), then Timer1's task will take 32 usec to complete a single calculation. QED SOL. -- Rich Webb Norfolk, VA
From: karthikbalaguru on 6 Dec 2009 12:07 On Dec 5, 10:13 pm, Rich Webb <bbew...(a)mapson.nozirev.ten> wrote: > On Sat, 05 Dec 2009 09:08:50 -0600, "thiru_vid" <thiru_...(a)yahoo.co.in> > wrote: > > > > > > >Timer1 ISR > > _______________________________________________________________ > >| | > >| |___________ > ><----Do some calculation it takes around 8us with in timer 1--> > ><--------- Each and every 10us, the timer 1 ISR is executed > >-----------> > > >Timer 3 ISR > > _________ _________ ________ _________ ________ > >| | | | | | | | | | |_____| |_____| > >|______| |_____| | > ><---1.5---> > ><-----2us-------> > > >I am using TMS320F2812 microcontroller. > >i need to implement the timer 3 ISR are executed within Timer 1 ISR. Is it > >possible to implement the same? > >Any one can you please help me for that. > > A dual core? An FPGA? Otherwise, as described, I don't see it as > possible. If Timer3 preempts Timer1, leaving 0.5 usec out of every 2.0 > usec available for Timer1 (not counting overhead), then Timer1's task > will take 32 usec to complete a single calculation. QED SOL. > But, if there is no preemption, then it should be feasible as Timer3 occurs every 2 us while Timer1 occurs only every 10us. But, i wonder how it will be able to function when it is in the 5th interval because during that scenario/occassion, timer3 and timer1 will both be trying to get executed and some kind of racing might happen . Any ideas ? Karthik Balaguru
From: Geek on 6 Dec 2009 13:25 Yes Use software interrupt priority. You must use Software Prioritized Interrupt PIE Block Specific Support Files. Read SPRC097.
From: Rich Webb on 6 Dec 2009 14:41
On Sun, 6 Dec 2009 09:07:27 -0800 (PST), karthikbalaguru <karthikbalaguru79(a)gmail.com> wrote: >On Dec 5, 10:13�pm, Rich Webb <bbew...(a)mapson.nozirev.ten> wrote: >> On Sat, 05 Dec 2009 09:08:50 -0600, "thiru_vid" <thiru_...(a)yahoo.co.in> >> wrote: >> >> >> >> >> >> >Timer1 ISR >> > _______________________________________________________________ >> >| � � � � � � � � � � � � � � � � � � � � � � � � � � � � � | � � � � � >> >| � � � � � � � � � � � � � � � � � � � � � � � � � � � � � |___________ � � � � � � � � � � >> ><----Do some calculation it takes around 8us with in timer 1--> >> ><--------- � �Each and every 10us, the timer 1 ISR is executed � >> >-----------> >> >> >Timer 3 ISR >> > _________ � _________ � � � ________ � � � �_________ � � � ________ >> >| � � | � � | � � � � | � � | � � � �| � � �| � � � � | � � | � � � � � �| � �|_____| � � � � |_____| � � � >> >|______| � � �|_____| � � � �| >> ><---1.5---> >> ><-----2us-------> >> >> >I am using TMS320F2812 microcontroller. >> >i need to implement the timer 3 ISR are executed within Timer 1 ISR. Is it >> >possible to implement the same? >> >Any one can you please help me for that. >> >> A dual core? An FPGA? Otherwise, as described, I don't see it as >> possible. If Timer3 preempts Timer1, leaving 0.5 usec out of every 2.0 >> usec available for Timer1 (not counting overhead), then Timer1's task >> will take 32 usec to complete a single calculation. QED SOL. >> >But, if there is no preemption, then it should be feasible as >Timer3 occurs every 2 us while Timer1 occurs only every 10us. If there is no preemption, then Timer3 won't be executed within Timer1. If there is, Timer1 won't complete its 8 usecs of calculations before the Timer1 interrupt fires again. One or the other, not both. -- Rich Webb Norfolk, VA |