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From: Ulf Samuelsson on 18 Dec 2009 19:13
-jg skrev 2009-12-17 09:41:
> On Dec 17, 2:11 pm, "Bill Giovino"<contac...(a)microcontroller-
> nospam.com> wrote:
>
>> This might be the lowest-power Cortex-M3 yet (I haven't seen the specs on ALL of them!).
>>
> Lowest power one starting with 'A' and ending with 'L'
> perhaps.
>
> In a real contest, it is clearly NOT the lowest power M3
>
> See
> http://www.energymicro.com/
>
> -jg
>

You have to be a little careful with the M3 and power consumption.
You can claim that you are running instructions from flash, when you are
executing
the "Wait for event" instruction.
This turns off the clock to the CPU until the event occurs, so it is really
not showing the real power consumption of the device if you measure
while the device is running that instruction..

Someone told me that NXP is playing or has played that game,
but I do not know if Energy Micro is doing that.

The device has 100% focus on power consumption.
You always have a choice between performance and power consumption
when you select the standard cell library.
They have clearly reasoned that the M3 has more
performance than whats needed in many applications, and they
decide to favour power consumption over performance in every case

This means that it really is competing with 8 bit devices in performance.
Max clock frequency is 32 MHz and above 16 MHz you add waitstates.
it looks to me that you add waitstates even for sequential fetches
so your 1,25 MIPS/MHz becomes a lot less.
Don't know if it drops to half, like on an ARM7TDMI, but ~20 MIPS
seems to be the max performance.

The SAM3S has a programmable 64 or 128 bit internal flash bus,
and runs at 64 MHz, so it is probably 3 x faster.
Really two different chips for two different markets.

--
Best Regards
Ulf Samuelsson
These are my own personal opinions, which may
or may not be shared by my employer Atmel Nordic AB

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