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From: =?ISO-8859-1?Q?Niels_J=F8rgen_Kruse?= on 14 Oct 2006 03:44
Wes Felter <wesley(a)felter.org> wrote:

> On 2006-10-12 15:38:04 -0500, nospam(a)ab-katrinedal.dk (Niels J?rgen
> Kruse) said:
>
> > The POWER6 has 32 MB of offdie cache too
> > (80GB/second bandwidth). Since the amount is a reduction from POWER5 and
> > IBM has discontinued their eDRAM in 65 nm, I guess this must be SRAM.
>
> Who says the L3 is 65nm? Maybe it's 90nm.

Why not go 65nm and double capacity then?

> And my reading of the slides shows two 32MB L3 chips, for 64MB total.

You interpret "32MB Non-sectored L3 Cache per chip" as "per cache chip".
That would explain the 2X on every bus to the L3 cache. I had read it as
"per CPU chip", which is natural as it is just below "per Core".

BTW, "Corona" is that the name of the cache chip?

> Did you really think they would reduce the L3 size from POWER5?

That was a bit strange, but elimination of sectoring would offer
compensation. The capacity of each cache chip is reduced though,
regardless of the number of them.

--
Mvh./Regards, Niels J?rgen Kruse, Vanl?se, Denmark
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