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From: Skybuck Flying on 17 May 2010 12:48
Hello,

The intel manual "The IA-32 Intel Architecture Software Developer's Manual,
Volume 2A, Instruction Set Reference, A-M, Document Number 253666 rev
19.pdf"

mentions LOCK prefix is available for the BTC, BTR, BTS instructions but it
doesn't mention it for BT instruction ?!?

Is this correct ? Is there truely no LOCK prefix for the BT instruction ?

If it's correct then my next question is:

Why is there no LOCK prefix for BT instruction ???

Bye,
Skybuck.


From: Frank Kotler on 17 May 2010 13:18
Skybuck Flying wrote:

....
> Why is there no LOCK prefix for BT instruction ???

Doesn't write anything... why would you want a "lock" prefix?

Best,
Frank

From: Alexei A. Frounze on 17 May 2010 13:21
On May 17, 10:18 am, Frank Kotler <fbkot...(a)myfairpoint.net> wrote:
> Skybuck Flying wrote:
>
> ...
>
> > Why is there no LOCK prefix for BT instruction ???
>
> Doesn't write anything... why would you want a "lock" prefix?

Exactly. And it needs to read just the byte containing the bit of
interest, in which case it doesn't even matter if another thread on a
different processor modifies a (d|q)word containing it. BT is gonna be
atomic anyways.

Alex
From: MitchAlsup on 17 May 2010 17:16
On May 17, 11:48 am, "Skybuck Flying" <IntoTheFut...(a)hotmail.com>
wrote:
> Why is there no LOCK prefix for BT instruction ???

What functionality do you think would a LOCK prefix add to BT anyways?
From: Skybuck Flying on 17 May 2010 19:05

"MitchAlsup" <MitchAlsup(a)aol.com> wrote in message
news:eb7ac133-0067-4c2c-bdda-338cc9c66b45(a)d12g2000vbr.googlegroups.com...
On May 17, 11:48 am, "Skybuck Flying" <IntoTheFut...(a)hotmail.com>
wrote:
> Why is there no LOCK prefix for BT instruction ???

"
What functionality do you think would a LOCK prefix add to BT anyways?
"

Suppose processor 1 has bit 5 in cache. (Bit 5 could be 0)

Suppose processor 2 has bit 5 in cache. (Bit 5 could be 1)

Processor 1 had bit 5 first.

Processor 2 had bit 5 second.

Maybe the system knows that processor 1 must update the memory from it's
cache first.

Then processor 2 must update the memory from it's cache next.

I was thinking maybe a LOCK will "flush" the processor's caches towards
memory ?

After which the BT instruction can execute on the memory to get a
consistent/updated view of the bit ?

Bye,
Skybuck.





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