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From: Vladimir Vassilevsky on 23 Jun 2010 06:17

On TI OMAP-L138 DSP, there is a system register which contains "DSP
reset vector" (HOST1CFG::DSP_ISTP_RST_VAL). For some reason, the lower
10 bits of this register are set to 0.

Is this the address from which the DSP starts executing, or is this a
pointer to memory location from which the DSP reads the starting address?

I couldn't find any explanation in the docs. Presented this question to
support; no answer.

VLV
From: Andreas Huennebeck on 23 Jun 2010 07:38
Vladimir Vassilevsky wrote:

>
> On TI OMAP-L138 DSP, there is a system register which contains "DSP
> reset vector" (HOST1CFG::DSP_ISTP_RST_VAL). For some reason, the lower
> 10 bits of this register are set to 0.

According to page 167 in SPRUGM7D (OMAP-L138 Applications Processor
System: Reference Guide, April 2010) these bits are reserved.

> Is this the address from which the DSP starts executing, or is this a
> pointer to memory location from which the DSP reads the starting address?

Maybe page 269 in SPRUGM7D gives a clue.

bye
Andreas
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From: Vladimir Vassilevsky on 23 Jun 2010 09:52


Andreas Huennebeck wrote:

> Vladimir Vassilevsky wrote:
>
>
>>On TI OMAP-L138 DSP, there is a system register which contains "DSP
>>reset vector" (HOST1CFG::DSP_ISTP_RST_VAL). For some reason, the lower
>>10 bits of this register are set to 0.
>
>
> According to page 167 in SPRUGM7D (OMAP-L138 Applications Processor
> System: Reference Guide, April 2010) these bits are reserved.

Reserved for what? It is supposed to be a 32-bit field. It could be
dword aligned, but why 10 bits?

>
>>Is this the address from which the DSP starts executing, or is this a
>>pointer to memory location from which the DSP reads the starting address?
>
>
> Maybe page 269 in SPRUGM7D gives a clue.

Been there, looks very confusing to me. As I can see, you are not sure
about the answer either.


VLV
From: Hans-Bernhard Bröker on 23 Jun 2010 10:12
Am 23.06.2010 15:52, schrieb Vladimir Vassilevsky:

> Reserved for what?

Oh come on, you surely know better than to ask that. It's reserved for
some other purpose than the current chip's documented usage. Could be
reserved for future use, reserved for factory internal testing, or
whatever. The crucial bit is that it's none of our business to worry
about it.

> It is supposed to be a 32-bit field. It could be dword aligned, but
> why 10 bits?

Because.
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