Oldschool TTL design question
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From: Bitrex on 5 Jan 2010 00:28 I've scored a huge bunch of 74LS series logic off Ebay, and since I'd like to learn more about digital design I'm thinking of building a classic digital clock circuit out of the logic. The assortment only contains 74LS93 4 bit counters, and I hope to use AND gates to decode the outputs to provide reset and clock pulses at the appropriate times. While the circuit simulates fine in the HADES software, my concern is that since the 74LS93 is a ripple counter the outputs will glitch and make this setup unusable in practice. In the "TTL Cookbook" the author states that some ripple counter states are glitch free, while others will cause problems, but doesn't seem to clarify the issue. I'm wondering if anyone here with more experience could tell if this kind of circuit is doomed to failure, or if it could work. The shipment hasn't arrived yet so unfortunately I can't set up a prototype just yet. Thanks for any advice!
From: John Larkin on 5 Jan 2010 01:07 On Tue, 05 Jan 2010 00:28:50 -0500, Bitrex <bitrex(a)de.lete.earthlink.net> wrote: >I've scored a huge bunch of 74LS series logic off Ebay, and since I'd >like to learn more about digital design I'm thinking of building a >classic digital clock circuit out of the logic. The assortment only >contains 74LS93 4 bit counters, and I hope to use AND gates to decode >the outputs to provide reset and clock pulses at the appropriate times. > While the circuit simulates fine in the HADES software, my concern is >that since the 74LS93 is a ripple counter the outputs will glitch and >make this setup unusable in practice. In the "TTL Cookbook" the author >states that some ripple counter states are glitch free, while others >will cause problems, but doesn't seem to clarify the issue. I'm >wondering if anyone here with more experience could tell if this kind of >circuit is doomed to failure, or if it could work. The shipment hasn't >arrived yet so unfortunately I can't set up a prototype just yet. >Thanks for any advice! If you use a NAND gate to decode a state of a ripple counter (for example, run Q2 and Q8 into the gate to decode "10" and reset the counter there, to count from 0 to 9) that decode is glitch-free. No state below 10 produces an output. John
From: Bitrex on 5 Jan 2010 02:21 John Larkin wrote: > On Tue, 05 Jan 2010 00:28:50 -0500, Bitrex > <bitrex(a)de.lete.earthlink.net> wrote: > >> I've scored a huge bunch of 74LS series logic off Ebay, and since I'd >> like to learn more about digital design I'm thinking of building a >> classic digital clock circuit out of the logic. The assortment only >> contains 74LS93 4 bit counters, and I hope to use AND gates to decode >> the outputs to provide reset and clock pulses at the appropriate times. >> While the circuit simulates fine in the HADES software, my concern is >> that since the 74LS93 is a ripple counter the outputs will glitch and >> make this setup unusable in practice. In the "TTL Cookbook" the author >> states that some ripple counter states are glitch free, while others >> will cause problems, but doesn't seem to clarify the issue. I'm >> wondering if anyone here with more experience could tell if this kind of >> circuit is doomed to failure, or if it could work. The shipment hasn't >> arrived yet so unfortunately I can't set up a prototype just yet. >> Thanks for any advice! > > If you use a NAND gate to decode a state of a ripple counter (for > example, run Q2 and Q8 into the gate to decode "10" and reset the > counter there, to count from 0 to 9) that decode is glitch-free. No > state below 10 produces an output. > > John > Thanks for the reply. Since the LS93 requires a positive trigger to reset, this should still work if I invert the outputs, correct? While I've constructed the functional equivalent of an AND gate, it would be the NAND part of it that's getting the glitches, if that makes any sense. It's really a NOT-NAND gate I guess.
From: markp on 5 Jan 2010 06:19 "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message news:vjl5k5pm9g2ed2ujd88i58av2qs1qc8qk0(a)4ax.com... > On Tue, 05 Jan 2010 00:28:50 -0500, Bitrex > <bitrex(a)de.lete.earthlink.net> wrote: > >>I've scored a huge bunch of 74LS series logic off Ebay, and since I'd >>like to learn more about digital design I'm thinking of building a >>classic digital clock circuit out of the logic. The assortment only >>contains 74LS93 4 bit counters, and I hope to use AND gates to decode >>the outputs to provide reset and clock pulses at the appropriate times. >> While the circuit simulates fine in the HADES software, my concern is >>that since the 74LS93 is a ripple counter the outputs will glitch and >>make this setup unusable in practice. In the "TTL Cookbook" the author >>states that some ripple counter states are glitch free, while others >>will cause problems, but doesn't seem to clarify the issue. I'm >>wondering if anyone here with more experience could tell if this kind of >>circuit is doomed to failure, or if it could work. The shipment hasn't >>arrived yet so unfortunately I can't set up a prototype just yet. >>Thanks for any advice! > > If you use a NAND gate to decode a state of a ripple counter (for > example, run Q2 and Q8 into the gate to decode "10" and reset the > counter there, to count from 0 to 9) that decode is glitch-free. No > state below 10 produces an output. > > John > And you can always put inverse of the clock into the NAND gate so that it only activated when the clock is low. As long as the propagation delay of the ripple counter is less than half a clock period (or more accurately less than the high time of the clock) you are assured a glitch free output. The techique you described above works well for simple modulo counters but if you are decoding other states as well the reset may well cause glitches on those signals when the counter is reset as some bits will reset before others. Mark.
From: markp on 5 Jan 2010 06:29
"markp" <map.nospam(a)f2s.com> wrote in message news:7qglfbF3faU1(a)mid.individual.net... > > "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in > message news:vjl5k5pm9g2ed2ujd88i58av2qs1qc8qk0(a)4ax.com... >> On Tue, 05 Jan 2010 00:28:50 -0500, Bitrex >> <bitrex(a)de.lete.earthlink.net> wrote: >> >>>I've scored a huge bunch of 74LS series logic off Ebay, and since I'd >>>like to learn more about digital design I'm thinking of building a >>>classic digital clock circuit out of the logic. The assortment only >>>contains 74LS93 4 bit counters, and I hope to use AND gates to decode >>>the outputs to provide reset and clock pulses at the appropriate times. >>> While the circuit simulates fine in the HADES software, my concern is >>>that since the 74LS93 is a ripple counter the outputs will glitch and >>>make this setup unusable in practice. In the "TTL Cookbook" the author >>>states that some ripple counter states are glitch free, while others >>>will cause problems, but doesn't seem to clarify the issue. I'm >>>wondering if anyone here with more experience could tell if this kind of >>>circuit is doomed to failure, or if it could work. The shipment hasn't >>>arrived yet so unfortunately I can't set up a prototype just yet. >>>Thanks for any advice! >> >> If you use a NAND gate to decode a state of a ripple counter (for >> example, run Q2 and Q8 into the gate to decode "10" and reset the >> counter there, to count from 0 to 9) that decode is glitch-free. No >> state below 10 produces an output. >> >> John >> > > And you can always put inverse of the clock into the NAND gate so that it > only activated when the clock is low. As long as the propagation delay of > the ripple counter is less than half a clock period (or more accurately > less than the high time of the clock) you are assured a glitch free > output. The techique you described above works well for simple modulo > counters but if you are decoding other states as well the reset may well > cause glitches on those signals when the counter is reset as some bits > will reset before others. > > Mark. > Sorry, you should of cource put the clock itself into the NAND gate, not its inverse :) Mark. |