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From: Xiao Guangrong on 15 Mar 2010 22:30 The RSV bit is possibility set in error code when #PF occurred only if CR4.PSE=1 or CR4.PAE=1 Signed-off-by: Xiao Guangrong <xiaoguangrong(a)cn.fujitsu.com> --- arch/x86/kvm/mmu.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 741373e..36e50ab 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2270,6 +2270,9 @@ static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) { int bit7; + if (!is_pae(vcpu) && !is_pse(vcpu)) + return 0; + bit7 = (gpte >> 7) & 1; return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; } -- 1.6.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ |