Prev: [PATCH] x86/mrst/pci: avoid enabling intx for msi capable devices
Next: x86/mrst/pci: avoid enabling intx for msi capable devices
From: Corinna Schultz on 21 Jun 2010 14:50
There was a small difference in 35-rc3 that prevented this patch from
applying, so I regenerated it.

===============================

Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so
bump the
limits up and provide an explanation of the requirements for each class.

Signed-off-by: Darrick J. Wong <djwong(a)us.ibm.com>
Acked-by: Muli Ben-Yehuda <muli(a)il.ibm.com>

--- a/arch/x86/kernel/pci_calgary_64.c 2010-06-21 10:57:15.000000000 -0700
+++ b/arch/x86/kernel/pci_calgary_64.c 2010-06-21 11:01:56.000000000 -0700
@@ -103,10 +103,15 @@
#define PMR_SOFTSTOPFAULT 0x40000000
#define PMR_HARDSTOP 0x20000000

-#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS 8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS *
MAX_NUM_CHASSIS * 2)
+/*
+ * The maximum PHB bus number.
+ * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+ * x3950M2: 4 chassis, 48 PHBs per chassis = 192
+ * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
+ * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
+ */
+#define MAX_PHB_BUS_NUM 384
+
#define PHBS_PER_CALGARY 4

/* register offsets in Calgary's internal register space */





--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo(a)vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
 | 
Pages: 1
Prev: [PATCH] x86/mrst/pci: avoid enabling intx for msi capable devices
Next: x86/mrst/pci: avoid enabling intx for msi capable devices