PCI-E chips
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From: David Lesher on 28 Nov 2009 13:52 I've been reading the basics of the PCI-E interface. Unlike PCI-nonE, which is parallel; PCI-E is serial, with slots/cards having 2^n, for n=0-5, serial "lanes" connecting them. A card can have less, equal or more lanes than the socket, except for physical space limits. [The socket may be 4 lanes wide; an 8 lane card won't fit. But it could be an 8-lane socket with only 4 implimented.] The motherboard/card automagically negotiate how many lanes work with a card. Further, newer lanes runs at higher bitrates than older ones, but can fall back for compatability. Besides flexibility, the serial scheme negates the issue of clock skew; it can handle one lane's data arriving later than others, etc. Then there's some kind of crosspoint switch that gets the data where you want it. I'm told that SATA data gets similar treatment. I don't know if USB and FireWire also do. My curiousity is that switch. With a say 6 slot motherboard, 3 slots being 32 wide, and one each 16, 8 and 2.... add in the 4 SATA channels and ???, and you have a LOT of channels into that crosspoint switch. And at the coming 1GB/s rate per lane; that's a lots of bits. How big are those crosspoint chips, anyhow? -- A host is a host from coast to coast.................wb8foz(a)nrk.com & no one will talk to a host that's close........[v].(301) 56-LINUX Unless the host (that isn't close).........................pob 1433 is busy, hung or dead....................................20915-1433
From: Jamie on 28 Nov 2009 14:31 David Lesher wrote: > I've been reading the basics of the PCI-E interface. Unlike PCI-nonE, > which is parallel; PCI-E is serial, with slots/cards having 2^n, for n=0-5, > serial "lanes" connecting them. > > A card can have less, equal or more lanes than the socket, except for > physical space limits. [The socket may be 4 lanes wide; an 8 lane card > won't fit. But it could be an 8-lane socket with only 4 implimented.] > > The motherboard/card automagically negotiate how many lanes work > with a card. Further, newer lanes runs at higher bitrates than > older ones, but can fall back for compatability. > > Besides flexibility, the serial scheme negates the issue of clock > skew; it can handle one lane's data arriving later than others, > etc. > > Then there's some kind of crosspoint switch that gets the data where you > want it. I'm told that SATA data gets similar treatment. I don't know > if USB and FireWire also do. > > My curiousity is that switch. With a say 6 slot motherboard, 3 slots > being 32 wide, and one each 16, 8 and 2.... add in the 4 SATA channels > and ???, and you have a LOT of channels into that crosspoint switch. And > at the coming 1GB/s rate per lane; that's a lots of bits. > > How big are those crosspoint chips, anyhow? > Sounds like you may be talking about the original micro channel idea from the days of the Micro channel technology from IBM.. Or maybe it's not?
From: Jon Slaughter on 28 Nov 2009 16:17 David Lesher wrote: > I've been reading the basics of the PCI-E interface. Unlike PCI-nonE, > which is parallel; PCI-E is serial, with slots/cards having 2^n, for > n=0-5, serial "lanes" connecting them. > > A card can have less, equal or more lanes than the socket, except for > physical space limits. [The socket may be 4 lanes wide; an 8 lane card > won't fit. But it could be an 8-lane socket with only 4 implimented.] > > The motherboard/card automagically negotiate how many lanes work > with a card. Further, newer lanes runs at higher bitrates than > older ones, but can fall back for compatability. > > Besides flexibility, the serial scheme negates the issue of clock > skew; it can handle one lane's data arriving later than others, > etc. > > Then there's some kind of crosspoint switch that gets the data where > you want it. I'm told that SATA data gets similar treatment. I don't > know > if USB and FireWire also do. > > My curiousity is that switch. With a say 6 slot motherboard, 3 slots > being 32 wide, and one each 16, 8 and 2.... add in the 4 SATA channels > and ???, and you have a LOT of channels into that crosspoint switch. > And at the coming 1GB/s rate per lane; that's a lots of bits. > > How big are those crosspoint chips, anyhow? Each lane cannot be arbitrarily connected to any other lane on the bus. Also there are only a fixed number of lanes(I think 64 for 2.0). This is why two video cards, even though both are x16, will only run at x8 each. One gets half the lanes and the other gets the other half. Ultimately the pci-e data is packetized and put on the internal bus just as any other data is. The lanes are simply there to replace a normal parallel bus since it modular. One can remove or add lanes without issue. Interally the device sending data across it just sees less latency when more lanes are in use. " In its early implementations, motherboards capable of SLI required a special card ("paddle card") which came with the motherboard. This card would fit into a socket usually located between both of the PCI-Express x16 slots. Depending on which way the card was inserted, the motherboard would either channel all 16 lanes into the primary PCI-Express x16 slot, or split lanes equally to both PCI-Express x16 slots. This was necessary as no motherboard at that time had enough PCI-Express lanes for both to have 16 lanes each. With the increase in available PCI-Express lanes, most modern SLI-capable motherboards allow each video card to use all 16 lanes in both PCI-Express x16 slots. The SLI bridge is used to reduce bandwidth constraints and send data between both graphics cards directly. It is possible to run SLI without using the bridge connector on a pair of low-end to mid-range graphics cards (e.g. 7100GS or 6600GT) with Nvidia's Forceware drivers 80.XX or later. Since these graphics cards do not use as much bandwidth, data can be relayed through just the chipsets on the motherboard. However, if no SLI bridge is used on two high-end graphics cards, the performance suffers severely as the chipset does not have enough bandwidth."
From: David Lesher on 28 Nov 2009 19:41
"Jon Slaughter" <Jon_Slaughter(a)Hotmail.com> writes: >> How big are those crosspoint chips, anyhow? >Also there are only a fixed number of lanes(I think 64 for 2.0). This >is why two video cards, even though both are x16, will only run at x8 >each. Hmm, I've not seen that limit before. One aspect I can really cheer over is the two-way backward compatabilty. Not only can a PCIE2 motherboard slot accept PCIE1 cards; but a PCIE1 motherboard can accept PCIE2 cards. Ditto for PCIE3.... the autodiscovery negotiates all. Someone, somewhere, REALLY had their head on straight on that one. No more of this "It's PCI, but you have the wrong voltage on that socket" and so forth. -- A host is a host from coast to coast.................wb8foz(a)nrk.com & no one will talk to a host that's close........[v].(301) 56-LINUX Unless the host (that isn't close).........................pob 1433 is busy, hung or dead....................................20915-1433 |