PHY initialization
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From: Mark on 24 Feb 2010 02:46 Hello my question is rather general - does an Ethernet PHY chip require any additional initialization upon hardware reset or it is always platform specific? I'm asking this because I'm having a problem reading/writing registers of PHY chip from my code; the chip is wired to a ethernet SoC via S3MII bus. I just try to understand: am I missing something more fundamental or should go through the SoC datasheet ince again. Thanks. -- Mark
From: Stef on 24 Feb 2010 03:43 In comp.arch.embedded, Mark <mark_cruzNOTFORSPAM(a)hotmail.com> wrote: > Hello > > my question is rather general - does an Ethernet PHY chip require any > additional initialization upon hardware reset or it is always platform > specific? > I'm asking this because I'm having a problem reading/writing registers of > PHY chip from my code; the chip is wired to a ethernet SoC via S3MII bus. I > just try to understand: am I missing something more fundamental or should go > through the SoC datasheet ince again. You are using the management lines of the interface, not the RX/TX lines? The PHY will default to an address (0-31) on the management interface. The default address depends on the PHY and the way it's wired on the board (pull up and down). Check the PHY datasheet (or try all addresses). -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) I believe that professional wrestling is clean and everything else in the world is fixed. -- Frank Deford, sports writer
From: Boudewijn Dijkstra on 24 Feb 2010 03:44 Op Wed, 24 Feb 2010 08:46:18 +0100 schreef Mark <mark_cruzNOTFORSPAM(a)hotmail.com>: > Hello > > my question is rather general - does an Ethernet PHY chip require any > additional initialization upon hardware reset or it is always platform > specific? > I'm asking this because I'm having a problem reading/writing registers > of PHY chip from my code; the chip is wired to a ethernet SoC via S3MII > bus. I just try to understand: am I missing something more fundamental > or should go through the SoC datasheet ince again. Usually a software reset is performed to make sure that the Phy is in a sane state. Another useful read is the IEEE Std 802.3-2005, part 3; more specifically section 2, chapters 22 and 28. -- Gemaakt met Opera's revolutionaire e-mailprogramma: http://www.opera.com/mail/ (remove the obvious prefix to reply by mail)
From: Vladimir Vassilevsky on 24 Feb 2010 10:50 Mark wrote: > Hello > > my question is rather general - does an Ethernet PHY chip require any > additional initialization upon hardware reset or it is always platform > specific? Yes and No. * PHYs are standardised. * It is a good practice to initialize everything that you are using. * PHY is in the operable state by reset. There may be no need to alter any of the settings. > I'm asking this because I'm having a problem reading/writing registers > of PHY chip from my code; the chip is wired to a ethernet SoC via S3MII > bus. I just try to understand: am I missing something more fundamental > or should go through the SoC datasheet ince again. The S3MII interface must work; if it is not working, it is an indication of a problem. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
From: salimbaba on 23 Mar 2010 18:08 hey, i am having same sort of a problem . i am using spartan 3E FPGA board with LAN83C185 PHY. I want to make 100Base Tx connection but i dont know what's wrong here. I have written the initialization code but i can't read or write to PHY . The code simulates perfectly but when i burn the code on FPGA, it doesn't work.. kindly help me out. --------------------------------------- Posted through http://www.EmbeddedRelated.com
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