PLL jitter and tracking filters
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From: crasic on 16 Jun 2010 02:09 Hi all, I posted this topic over at comp.dsp and they suggested I try you guys. I'm working on a problem that requires a tracking bandpass filter. The center frequency is known a priori, but has some drift within the range 0.01-0.05 f. A typical frequency would be 700KHz with a corresponding 1-2Khz drift and fairly noisy which, after digitizing and edge detection, is in the form of frequency jitter, Ideally the center frequency should be easily set. The output of the circuit is essentially a square wave, with some predetermined (and preferably adjustable) pulse width. The signal drift is fairly small, ~+- 500Hz for the 700KHz signal. What we are worried about most is reducing jitter on the resultant square wave. We are currently successfully using a sequence of amplifiers, an analog (constant) bandpass, and a sine->square converter based on some 74XX chips. Unfortunately this analog circuitry is power hungry, expensive, nonconfigurable, and bulky. So we want to (if possible) move everything to the digital domain, ideally implemented on some programmable logic like an FPGA. So one idea is to use a purely digital PLL synthesized in an altera fpga. We are essentially using something like http://opencores.org/project,dpll_rwf but independently designed by me from the same references (not by choice, I stumbled on his open source design after the work was done). The DPLL design is based on some older IEEE papers (late 70's) and uses a binary phase detector and a sequential loop filter (a "Variable Reset Random Walk Filter" or "VR-RMF" in dsp jargon) which is essentially two up/down counters hooked up in a clever way, We measured our noise floor with the PLL running in an open loop to be approximately ~50uHz at 700KHz and a 160Mhz (10*16) clock (all measurements are taken over 1 second. 10 readings are taken and averaged). About ten times better than our "ideal" output jitter of the running loop. As it turns out, the PLL is working too much as an ideal bandpass. On a scope you can see a clearly mimicked signal, i.e. it is following the input signal with all its jitter and the output jitter of the pll matches the input jitter (when measured on a frequency counter). The input and output jitter is 3 orders of magnitude above our intrinsic jitter of the loop so there is room for improvement. The paper which this design is based on (reference 3 on that open cores page) experimentally predicts frequency jitter reduction of ~5-10 fold over input jitter on a relatively noisy signal. We are getting almost no reduction. Does anyone have any thoughts on this problem with the PLL? Or maybe more generally: How would you approach the general problem stated at the top? Thanks for reading Andrey Shmakov University of California Berkeley Department of Physics
From: whit3rd on 16 Jun 2010 03:30 On Jun 15, 11:09 pm, crasic <trueurss...(a)gmail.com> wrote: > I'm working on a problem that requires a tracking bandpass filter. The > center frequency is known a priori, but has some drift within the > range 0.01-0.05 f. A typical frequency would be 700KHz with a > corresponding 1-2Khz drift and fairly noisy which, after digitizing > and edge detection, is in the form of frequency jitter, Ideally the > center frequency should be easily set. The output of the circuit is > essentially a square wave, with some predetermined (and preferably > adjustable) pulse width. > > The signal drift is fairly small, ~+- 500Hz for the 700KHz signal. > What we are worried about most is reducing jitter on the resultant > square wave. We are currently successfully using a sequence of > amplifiers, an analog (constant) bandpass, and a sine->square > converter based on some 74XX chips. > > Unfortunately this analog circuitry is power hungry, expensive, > nonconfigurable, and bulky. So we want to (if possible) move > everything to the digital domain, ideally implemented on some > programmable logic like an FPGA. At 700 kHz, a CMOS 74HC4046 or 74HC9046 would do the job without much difficulty. If, by 'square wave' you mean your output is 50% duty cycle, it's maybe ALL you need. Not expensive, nor bulky, nor power-hungry, not at all. > So one idea is to use a purely digital PLL synthesized in an altera > fpga. But, what is the advantage of that? It's not clear what aspect of the input signal is significant, and what part is noise that can confuse the modulation. Jitter usually means edge-timing deviation from a perfect clock, and you could change the PLL loop filter to suppress cycle-to-cycle deviations if that were the only concern. If anything, a fast FPGA would sense a wide bandwidth of random noise and act on it, rather than suppressing out-of-band input. Digital PLL is great if your input is digital (like, self-clocked asynchronous data), but not for a high-purity sinewave (which has timing data AT ALL POINTS IN THE WAVEFORM, not just at the 'logic threshold' point).
From: Jeroen Belleman on 16 Jun 2010 03:43 crasic wrote: > I'm working on a problem that requires a tracking bandpass filter.[...] > What we are worried about most is reducing jitter on the resultant > square wave. [...] > > So one idea is to use a purely digital PLL synthesized in an altera > fpga. [...] > > As it turns out, the PLL is working too much as an ideal bandpass. On > a scope you can see a clearly mimicked signal, i.e. it is following > the input signal with all its jitter and the output jitter of the pll > matches the input jitter (when measured on a frequency counter). [...] At the risk of stating the obvious: If the spectrum of the jitter falls within the bandwidth of the loop filter, it will pass through the PLL unattenuated. You should reduce the loop filter bandwidth. Of course you may then run into tracking range problems... Jeroen Belleman
From: crasic on 16 Jun 2010 04:07 On Jun 16, 12:30 am, whit3rd <whit...(a)gmail.com> wrote: > At 700 kHz, a CMOS 74HC4046 or 74HC9046 would do the job without > much difficulty. If, by 'square wave' you mean your output > is 50% duty cycle, it's maybe ALL you need. Not expensive, nor > bulky, > nor power-hungry, not at all. > > > So one idea is to use a purely digital PLL synthesized in an altera > > fpga. > > But, what is the advantage of that? It's not clear what aspect of the > input signal is significant, and what part is noise that can confuse > the modulation. Jitter usually means edge-timing deviation from > a perfect clock, and you could change the PLL loop filter to > suppress cycle-to-cycle deviations if that were the only concern. > If anything, a fast FPGA would sense a wide bandwidth of random noise > and > act on it, rather than suppressing out-of-band input. > > Digital PLL is great if your input is digital (like, self-clocked > asynchronous > data), but not for a high-purity sinewave (which has timing data AT > ALL > POINTS IN THE WAVEFORM, not just at the 'logic threshold' point). The input frequency is the most significant, and what we are trying to extract and clean up. The "ideal" signal has very good short term stability, it drifts continuously over a long period of time (on the order of several seconds), but we haven't even gotten to real world signals yet. The test set up is simply a signal generator output that is attenuated, then amplified (to simulate a noisy signal), and then run through a sine->square converter. In our test set up we aren't even looking at tracking stability since the base frequency is constant and all noise induced is random. In principle the PLL should filter out the noise and reproduce (to some extent) our original signal. The reason behind using and FPGA is that there is a potential remote sensing application and being able to quickly and easily reconfigure or adjust parameters without having physical access to the board is very desirable. Andrey Shmakov University of California Berkeley Department of Physics
From: Phil Hobbs on 16 Jun 2010 07:32
crasic wrote: > On Jun 16, 12:30 am, whit3rd <whit...(a)gmail.com> wrote: >> At 700 kHz, a CMOS 74HC4046 or 74HC9046 would do the job without >> much difficulty. If, by 'square wave' you mean your output >> is 50% duty cycle, it's maybe ALL you need. Not expensive, nor >> bulky, >> nor power-hungry, not at all. >> >>> So one idea is to use a purely digital PLL synthesized in an altera >>> fpga. >> But, what is the advantage of that? It's not clear what aspect of the >> input signal is significant, and what part is noise that can confuse >> the modulation. Jitter usually means edge-timing deviation from >> a perfect clock, and you could change the PLL loop filter to >> suppress cycle-to-cycle deviations if that were the only concern. >> If anything, a fast FPGA would sense a wide bandwidth of random noise >> and >> act on it, rather than suppressing out-of-band input. >> >> Digital PLL is great if your input is digital (like, self-clocked >> asynchronous >> data), but not for a high-purity sinewave (which has timing data AT >> ALL >> POINTS IN THE WAVEFORM, not just at the 'logic threshold' point). > > The input frequency is the most significant, and what we are trying to > extract and clean up. The "ideal" signal has very good short term > stability, it drifts continuously over a long period of time (on the > order of several seconds), but we haven't even gotten to real world > signals yet. The test set up is simply a signal generator output that > is attenuated, then amplified (to simulate a noisy signal), and then > run through a sine->square converter. In our test set up we aren't > even looking at tracking stability since the base frequency is > constant and all noise induced is random. In principle the PLL should > filter out the noise and reproduce (to some extent) our original > signal. > > The reason behind using and FPGA is that there is a potential remote > sensing application and being able to quickly and easily reconfigure > or adjust parameters without having physical access to the board is > very desirable. > > Andrey Shmakov > University of California Berkeley > Department of Physics A 4046 and a DPOT? Horses for courses, and the amount of engineering time this seems to be taking up is pretty monumental for a university job! Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net |