Periodic instruction set testing - done it? heard of it?
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From: Dirk Zabel on 24 May 2010 13:00 KK6GM schrieb: > Over at avrfreaks.net the question of periodic instruction set testing > has come up, in particular as a requirement (apparently, it's not > exactly clear) in UL1998. I've never heard of such a thing. Can > anybody tell me anything about this subject, such as, is it actually > done, and if so, how? Reminds me of the "DIAGNOSTIC PROGRAM" card which whas contained in the standard pac for the programmable HP 67 and HP 97 calculator. It helped me when I wrote an HP 67 simulator for my late TI Avigo (now ported to a Palm Tungsten and still in use :-) ) -- Dirk
From: Not Really Me on 3 Jun 2010 11:22 KK6GM wrote: > Over at avrfreaks.net the question of periodic instruction set testing > has come up, in particular as a requirement (apparently, it's not > exactly clear) in UL1998. I've never heard of such a thing. Can > anybody tell me anything about this subject, such as, is it actually > done, and if so, how? > To the best of my knowledge this is not a UL1998 requirement. A similar concept comes up in IEC-61508 on "single channel" computers, but this is CPU testing, not specifically instruction set testing. Single channel in this case refers to products containing only a single CPU. For products needing high levels of criticality dual cpus are usually used. One acting as a sophisticated watch dog on the main CPU. More than instructions, CPU testing is typically looking for failures in bits in registers. A technique similar to memory testing is used at the register level. -- Scott Validated Software Lafayette, CO __________ Information from ESET NOD32 Antivirus, version of virus signature database 5169 (20100603) __________ The message was checked by ESET NOD32 Antivirus. http://www.eset.com
From: Walter Banks on 3 Jun 2010 15:12 Not Really Me wrote: > KK6GM wrote: > > Over at avrfreaks.net the question of periodic instruction set testing > > has come up, in particular as a requirement (apparently, it's not > > exactly clear) in UL1998. I've never heard of such a thing. Can > > anybody tell me anything about this subject, such as, is it actually > > done, and if so, how? > > > > To the best of my knowledge this is not a UL1998 requirement. A similar > concept comes up in IEC-61508 on "single channel" computers, but this is CPU > testing, not specifically instruction set testing. Single channel in this > case refers to products containing only a single CPU. For products needing > high levels of criticality dual cpus are usually used. One acting as a > sophisticated watch dog on the main CPU. > > More than instructions, CPU testing is typically looking for failures in > bits in registers. A technique similar to memory testing is used at the > register level. There are a variety of ways to produce a reliable computer. I do a lot of work with automotive processors. The processors need to work over a wide temperature range and in some very bad electrical environments (think of the transients while starting a cold engine) Part of the solution is processors that have error correcting registers. We are finding that some of the processors used in automotive are finding uses in other fields simply for the reliable operation. Regards, w.. -- Walter Banks Byte Craft Limited http://www.bytecraft.com
From: antedeluvian on 3 Jun 2010 15:29
>Over at avrfreaks.net the question of periodic instruction set testing >has come up, in particular as a requirement (apparently, it's not >exactly clear) in UL1998. I've never heard of such a thing. Can >anybody tell me anything about this subject, such as, is it actually >done, and if so, how? > When I worked on the Canadarm2 (the robotic manipulator on the International Space Station) there was a requirement that the CPU self-exercise the instruction set periodically. There was a redundant processor so the execution could be switched. I am pretty sure that this is common in space applications although I don't know if there is a MIL-STD or NASA standard that covers it. I only worked with the requirements so I am not sure how it was implemented especially since I was laid off when times got tight. -Aubrey --------------------------------------- Posted through http://www.EmbeddedRelated.com |