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From: Paul Keinanen on 21 Jun 2010 15:07
On Mon, 21 Jun 2010 04:20:09 -0700 (PDT), MooseFET
<kensmith(a)rahul.net> wrote:

>
>The trick is to make a very tight notch at the mains frequencies
>and use a normal low pass for the general junk.

Or even a comb filter at 10 Hz, that will take out both 50 and 60 Hz
(depending on location) and their harmonics.


>The first step is to make a PLL that locks onto the 60Hz. You want
>the VCO in the PLL to be running at many times the 60Hz frequency.
>I am going to suggest 7200 times, but faster is likely better. 7200
>times just makes the explanation easier.

The PLL would solve the network frequency drift during the day, which
can vary more than 1000 ppm, depending on the load.

From: Glenn Kenroy on 22 Jun 2010 07:44
On Mon, 21 Jun 2010 04:20:09 -0700 (PDT), MooseFET
<kensmith(a)rahul.net> wrote:

>The trick is to make a very tight notch at the mains frequencies
>and use a normal low pass for the general junk.
>
>The first step is to make a PLL that locks onto the 60Hz. You want
>the VCO in the PLL to be running at many times the 60Hz frequency.
>I am going to suggest 7200 times, but faster is likely better. 7200
>times just makes the explanation easier.
>
>Important frequencies:
>
>60*8*3*5 = 7200
>
>7200 / 15 = 60*8
>7200 / 3 = 5*60*8
>7200 / 5 = 3*60*8
>
>I will assume that you have the PLL locked to the 60Hz.
>
>
>You will be making the same circuit 3 times. It uses the CD4051
>The 8 times the frequency goes to a counter that makes the
>CD4051 scan through a group of capacitors.
>
>Each of the 8 outputs of the CD4051 connects to one end of
>a capacitor. The other end of the capacitor is grounded.
>
>If the common point is fed with a resistor. This makes a circuit
>that will charge up the capacitors until they match the 60Hz
>input waveform.

This appears to be the most promising response so far to the elusive
zero-delay issue.

What might it take for you to draw this up as a conceptual circuit
(untested OK) to get me started on the right track?

Glenn Kenroy

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