Reversing bit order in delphi ? (unmoderated)
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From: Rod Pemberton on 20 Aug 2006 02:28 "Skybuck" <skybuck2000(a)hotmail.com> wrote in message news:1155982608.221901.39950(a)p79g2000cwp.googlegroups.com... > > > I think intel uses most significant bit first ? > > > > No, Intel uses LSB (Least Significant Byte, i.e., Little Endian, where a > > byte is 8-bits, i.e., not a byte as defined by C) > > Oopsie you did not read my post well enough. > Wrong. I answered your erroneous question and corrected your confusion about bit order. Intel does not use most significant bit first, it uses LSB. > I really do mean bit order, not byte order. > Fair enough. We've now clarified that your original statements indicated you were confused over bit order and byte order... Rod Pemberton
From: Skybuck on 20 Aug 2006 04:47 f0dder schreef: > A 256-byte LUT can easily fit in any CPU L1 cache. Typically a cacheline is > 32 bytes long, so you'd maximally get (256/32) 8 cache misses before the > entire LUT is cached. I'm pretty sure that this is hard to beat no matter > which fancy instruction set you're going to use... Hello, Thank you for trying to explain it. I still do not quite understand it completely maybe you can clearify something: Does the above theory only apply to the xlat instruction or any instruction/memory access that uses the lookup table technique ? Bye, Skybuck.
From: Skybuck on 20 Aug 2006 06:17 Skybuck schreef: > Woops, sorry, I did not know comp.lang.asm.x86 is a moderated > newsgroup, as I don't like moderated newsgroups I post it again and > exclude comp.lang.asm.x86: > > Reversing bit order in delphi ? > > Hello, > > I think intel uses most significant bit first ? Nope, sorry, I was wrong. The byte order and bit order of data in RAM is both Little Endian for intel. (LSB) The byte order and bit order of CPU registers is both Little Endian for intel. (LSB) The drawing below was correct, but the comments are wrong. When transmitting bits and bytes intels reads from right to left. So intel starts reading at the lowest bit order/number. So that means least significant data bit/byte first. > [intel system, most significant bit first] Should be: [intel system, lest significant bit (and byte) first] Bye, Skybuck.
From: Skybuck on 20 Aug 2006 06:23 Rod Pemberton schreef: > "Skybuck" <skybuck2000(a)hotmail.com> wrote in message > news:1155982608.221901.39950(a)p79g2000cwp.googlegroups.com... > > > > I think intel uses most significant bit first ? > > > > > > No, Intel uses LSB (Least Significant Byte, i.e., Little Endian, where a > > > byte is 8-bits, i.e., not a byte as defined by C) > > > > Oopsie you did not read my post well enough. > > > > Wrong. I answered your erroneous question and corrected your confusion > about bit order. Intel does not use most significant bit first, it uses > LSB. > > > I really do mean bit order, not byte order. > > > > Fair enough. We've now clarified that your original statements indicated > you were confused over bit order and byte order... True, I did not know exactly what the thruth was. I just wanted to be able to flip the bits ;) I consulted the manual of intel and intel indeed uses LSB for both bit and byte order and for memory and registers. Intel starts reading from right to left. It starts reading at the lowest byte/bit order/number and this corresponds to the least significant bit and byte. Memory layout is: bit 31.... bit 0 byte 3..... byte 0 <--------------------- longword 10 /|\ | | longword 0 Register layout is: bit 31.... bit 0 byte 3.... byte 0 <--------------------- So intel reads from bottom to top so to speak and from right to left. Crazy lol. It's the world upside down ! ;) Bye, Skybuck :)
From: J French on 20 Aug 2006 06:39
On 20 Aug 2006 03:23:38 -0700, "Skybuck" <skybuck2000(a)hotmail.com> wrote: <snip> >Intel starts reading from right to left. It starts reading at the >lowest byte/bit order/number and this corresponds to the least >significant bit and byte. > >Memory layout is: > >bit 31.... bit 0 >byte 3..... byte 0 ><--------------------- >longword 10 >/|\ > | > | >longword 0 > >Register layout is: > >bit 31.... bit 0 >byte 3.... byte 0 ><--------------------- >So intel reads from bottom to top so to speak and from right to left. >Crazy lol. >It's the world upside down ! ;) No it makes a lot of sense If you have an unsigned 4 byte number, then the same number as an unsigned 2 byte number (or 1 byte number) is at the same location It makes it a heck of a lot easier reading in a number low part first You really need to learn a bit of ASM. Delphi's ASM support is very good (IMO) Once you get to understand the guts, things look pretty logical. |