SATA_SIL on IXP425 workaround
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From: Jeff Garzik on 21 Jan 2010 01:50 On 01/20/2010 11:58 PM, Jeff Garzik wrote: > On 01/14/2010 10:59 AM, Bartlomiej Zolnierkiewicz wrote: >> On Monday 09 November 2009 06:31:21 pm Krzysztof Halasa wrote: >>> I'm trying to add a workaround for IXP4xx CPUs to SATA SIL driver. The >>> problem is that IXP4xx CPUs (Intel's XScale (ARM) network-oriented >>> processors) are unable to perform 8 and 16-bit read from PCI MMIO, they >>> can only do a full 32-bit readl(); SIL chips respond to that with PCI >>> abort. The workaround is to use 8 and 16-bit regular IO reads (inb/inw) >>> instead (MMIO write is not a problem). >>> >>> For SIL3x12 the workaround is simple (attached) and it works on my 3512. >>> I'm not sure about 3114 (the 4-port chip) - the PIO BARs have TF, CTL >>> and BWDMA registers which are common to channels 0 and 2, and (the other >>> set) to channels 1 and 3. Channel selection is done with bit 4 of >>> device/head TF register, this is similar (same?) as PATA master/slave. >>> Does that mean that I can simply treat channel 0 as PRI master, ch#2 as >>> PRI slave, ch#1 as SEC master and ch#3 as SEC slave, and the SFF code >>> will select the right device correctly? Does it need additional code? >>> I don't have anything based on 3114. >>> >>> Note: the large PRD is not a problem here, the transfer can be started >>> by MMIO write. Only reads are an issue. >> >> FWIW your patch is now in my atang tree (I'm aware that Jeff is working >> on generic solution but in the meantime this non-intrusive patch allows >> sata_sil to work on IXP425). > > I was asking an open question, is a generic solution possible? > > Something like the attached patch might work, due it is completely > untested, and I did not verify that the BMDMA Status register is not > stomped. Also, the additional ioread32() calls in bmdma start/stop are > LIKELY to be unnecessary. As I suspected, there is a W1C register in there. But it does look possible to do all-32-bit accesses. Jeff -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Jeff Garzik on 21 Jan 2010 13:40 On 01/21/2010 01:48 AM, Jeff Garzik wrote: > On 01/20/2010 11:58 PM, Jeff Garzik wrote: >> On 01/14/2010 10:59 AM, Bartlomiej Zolnierkiewicz wrote: >>> On Monday 09 November 2009 06:31:21 pm Krzysztof Halasa wrote: >>>> I'm trying to add a workaround for IXP4xx CPUs to SATA SIL driver. The >>>> problem is that IXP4xx CPUs (Intel's XScale (ARM) network-oriented >>>> processors) are unable to perform 8 and 16-bit read from PCI MMIO, they >>>> can only do a full 32-bit readl(); SIL chips respond to that with PCI >>>> abort. The workaround is to use 8 and 16-bit regular IO reads (inb/inw) >>>> instead (MMIO write is not a problem). >>>> >>>> For SIL3x12 the workaround is simple (attached) and it works on my >>>> 3512. >>>> I'm not sure about 3114 (the 4-port chip) - the PIO BARs have TF, CTL >>>> and BWDMA registers which are common to channels 0 and 2, and (the >>>> other >>>> set) to channels 1 and 3. Channel selection is done with bit 4 of >>>> device/head TF register, this is similar (same?) as PATA master/slave. >>>> Does that mean that I can simply treat channel 0 as PRI master, ch#2 as >>>> PRI slave, ch#1 as SEC master and ch#3 as SEC slave, and the SFF code >>>> will select the right device correctly? Does it need additional code? >>>> I don't have anything based on 3114. >>>> >>>> Note: the large PRD is not a problem here, the transfer can be started >>>> by MMIO write. Only reads are an issue. >>> >>> FWIW your patch is now in my atang tree (I'm aware that Jeff is working >>> on generic solution but in the meantime this non-intrusive patch allows >>> sata_sil to work on IXP425). >> >> I was asking an open question, is a generic solution possible? >> >> Something like the attached patch might work, due it is completely >> untested, and I did not verify that the BMDMA Status register is not >> stomped. Also, the additional ioread32() calls in bmdma start/stop are >> LIKELY to be unnecessary. > > As I suspected, there is a W1C register in there. But it does look > possible to do all-32-bit accesses. It is definitely possible to do all 32-bit accesses... but that requires activating and exclusively using the command buffering feature, because direct 32-bit access to the taskfile registers will result in a 32-bit access to Data rather than the desired effect. The chip docs are at http://gkernel.sourceforge.net/specs/sii/ for those unfamiliar with my doc archive. Jeff -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
From: Krzysztof Halasa on 21 Jan 2010 16:50
Jeff Garzik <jeff(a)garzik.org> writes: > It is definitely possible to do all 32-bit accesses... but that > requires activating and exclusively using the command buffering > feature, because direct 32-bit access to the taskfile registers will > result in a 32-bit access to Data rather than the desired effect. Command buffering? The DS for SIL3512 lists IDEx taskfile registers for command buffering, but I can't see any explanation there. BTW I don't know requirements of other platforms, but IXP4xx has only problems with 8- and 16-bit PCI memory reads. Other ops including all memory writes, and all "port" I/O are ok. Unfortunately I can't test any patch ATM, -ENOHW. I might be able to get access to this hw again, but I don't know at this point. -- Krzysztof Halasa -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ |