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From: Andy 'Krazy' Glew on 1 Jun 2010 11:06
On 5/31/2010 7:02 PM, Paul A. Clayton wrote:
> On May 30, 11:18 am, Andy 'Krazy' Glew<ag-n...(a)patten-glew.net>
> wrote:
> [snip]
>> The original Pentium 4 ALUs were staggered in that they computed the low 16 bits in one of these fast clock cycles, and
>> the high in the next - allowing back to back adds. But that is not the widespread definition of "staggered" ALU.
>
> I took the term from "Using Internal Redundant Representations and
> Limited Bypass to Support Pipelined Adders and Register Files"
> (Mary D. Brown, Yale N. Patt; 2001 [HPCA-3]):
> "An example of this concept, called staggered adds, was
> implemented in the Intel Pentium 4 [10]. When staggering a 32-bit
> add over two cycles, the carry-out of the 16th bit and the lower half
> of the result are produced in the first cycle, and the upper half of
> the
> result is produced in the second cycle."
>
> So what is the proper term for this kind of pipelined addition?


I apologize.

Apparently the Willamette team was using the term "staggered ALU",
e.g. in paper http://www.dre.vanderbilt.edu/~aky/My/ppt/The%20Microarchitecture%20of%20Pentium%204%20Processor.pdf

This use is scattered all over the Internet, in lots of class notes.

(I used the term "width pipelined", but that was really early in the life of Willamette.)

Apparently the ALUs that are set to cascade from one to the other within a clock cycle are more commonly called cascaded
ALUs.


Terms for my lexicon.
From: Paul A. Clayton on 1 Jun 2010 14:44
On Jun 1, 11:06 am, Andy 'Krazy' Glew <ag-n...(a)patten-glew.net> wrote:
[snip]
> I apologize.

Well, this ended up helping both of us.

> Apparently the Willamette team was using the term "staggered ALU",
> e.g. in paperhttp://www.dre.vanderbilt.edu/~aky/My/ppt/The%20Microarchitecture%20o...
>
> This use is scattered all over the Internet, in lots of class notes.
>
> (I used the term "width pipelined", but that was really early in the life of Willamette.)
>
> Apparently the ALUs that are set to cascade from one to the other within a clock cycle are more commonly called cascaded
> ALUs.
>
> Terms for my lexicon.

Thank you for the research (and personal history)!

Perhaps a lexicon/list of abbreviations might be appropriate for your
CompArch wiki. (Thank you also for this donation.)


Paul A. Clayton
just a technophile
From: Andy 'Krazy' Glew on 2 Jun 2010 00:21
On 6/1/2010 11:44 AM, Paul A. Clayton wrote:
> On Jun 1, 11:06 am, Andy 'Krazy' Glew<ag-n...(a)patten-glew.net> wrote:
> [snip]
>> I apologize.
>
> Well, this ended up helping both of us.
>
>> Apparently the Willamette team was using the term "staggered ALU",
>> e.g. in paperhttp://www.dre.vanderbilt.edu/~aky/My/ppt/The%20Microarchitecture%20o...
>>
>> This use is scattered all over the Internet, in lots of class notes.
>>
>> (I used the term "width pipelined", but that was really early in the life of Willamette.)
>>
>> Apparently the ALUs that are set to cascade from one to the other within a clock cycle are more commonly called cascaded
>> ALUs.
>>
>> Terms for my lexicon.
>
> Thank you for the research (and personal history)!
>
> Perhaps a lexicon/list of abbreviations might be appropriate for your
> CompArch wiki. (Thank you also for this donation.)


Yep. Although I must admit that I have a bit of trouble with the wiki organization in this regard. I find it hard to
define terms in isolation - I often want to define terms via little essays that compare them to related terms.

In my dreams, I rewrite the wiki software so that such terms can easily forward to discussion pages. But mediawiki's
redirection technology is quite primitive, so I think a rewrite is needed. But that is lower priority than me getting
the ability to edit diagrams onto the comp-arch.net wiki.

By the way, in case anyone is interested: my current direction in diagram editing is SVG-edit.

From: Andy 'Krazy' Glew on 2 Jun 2010 01:51
On 6/1/2010 9:21 PM, Andy 'Krazy' Glew wrote:
> On 6/1/2010 11:44 AM, Paul A. Clayton wrote:
>> On Jun 1, 11:06 am, Andy 'Krazy' Glew<ag-n...(a)patten-glew.net> wrote:
>> [snip]
>>> I apologize.
>>
>> Well, this ended up helping both of us.
>>
>>> Apparently the Willamette team was using the term "staggered ALU",
>>> e.g. in
>>> paperhttp://www.dre.vanderbilt.edu/~aky/My/ppt/The%20Microarchitecture%20o...
>>>
>>>
>>> This use is scattered all over the Internet, in lots of class notes.
>>>
>>> (I used the term "width pipelined", but that was really early in the
>>> life of Willamette.)
>>>
>>> Apparently the ALUs that are set to cascade from one to the other
>>> within a clock cycle are more commonly called cascaded
>>> ALUs.
>>>
>>> Terms for my lexicon.
>>
>> Thank you for the research (and personal history)!
>>
>> Perhaps a lexicon/list of abbreviations might be appropriate for your
>> CompArch wiki. (Thank you also for this donation.)

You made me do it:

https://semipublic.comp-arch.net/wiki/Cascaded_ALUs
https://semipublic.comp-arch.net/wiki/Staggered_ALUs
https://semipublic.comp-arch.net/wiki/Width-pipelined_ALUs

If I write a page every evening, I may be finished before I get senile.
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