SPI communication problem with Si3215 & AT91SAM7SE256
in [Embedded]
|
From: RockyG on 26 Apr 2010 01:33 >And BTW, how does my question on the maximum input current suggest that I >am a beginner in embedded electronics? Probably because CMOS inputs draw very little current, even taking into accoutn the input capacitance. The 4MHz clock is not an issue, it is the rise an fall times that cause problems due to reflections. For some interesting reading have a look at the Blckfin SPI documentation. It could be that using the HC125 is improving performand because it has slightly slower rise times that the CPU. As Frank says, try series resitors in the SCLK and MOSI signals. I would suggest values more like 100 ohms, but it may be worth experimenting. --------------------------------------- Posted through http://www.EmbeddedRelated.com
From: Stef on 26 Apr 2010 04:20 In comp.arch.embedded, faiyaz <faiyaz.pw(a)n_o_s_p_a_m.gmail.com> wrote: > > And BTW, how does my question on the maximum input current suggest that I > am a beginner in embedded electronics? Because the current you mentioned (10 mA IIRC) must be in the "absolute maximum ratings" section of the datasheet. That means it is the maximum current allowed to flow in the pin before it goes up in smoke. Such a current will only flow if the input voltage is higher than the supply voltage. It is most likely the maximum rating for the input clamping diodes. For the actual input current under normal conditions, look in the operational data section of the datasheet. There may be something like "input leakage current", probably in the uA range. This is the static current the input will draw (or supply, a lot of times the figure is +/-). But as another poster said, the current through the input capacitance will likely be higher at your clock frequency than the static input current.. And I think you can drop the 'embedded' from your question above. Based on that question, you seem to be a beginner in electronics. ;-) When driving a large number of chips with a single clock, there are likely to be a lot of reflections, which may mess up your signal. You may also have problems with the large capacitive load on the signal. Both problems should be less of a problem if you lower the clock frequency, so that's worth a try. Both problems can be simulated and/or measured with a scope. If you use a scope, watch the input capacitance of your probe an make sure the ground connection is really short. Use the ground ring at the probe tip to touch a ground very close to the signal you are measuring. Just using the probe's alligator clip ground wire will most likely make you see ringing signals where there are none. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) A mushroom cloud has no silver lining.
From: faiyaz on 27 Apr 2010 07:42
Hi RockyG, I applied your suggestion of using series resistors on Clock & MOSI signals. I used 50 Ohm series resistors on both signals and i can now observe that the problem of Ringing & Overshoot is significantly reduced. I also tried reducing the SPI clock upto 500 KHz. But the problem remains there as it is... & Thanks Stef and RockyG for the info regarding the digital inputs and CMOS charactersitics. I just wanted to gain the knowledge that is why I asked.. Thanks Faiyaz --------------------------------------- Posted through http://www.EmbeddedRelated.com |