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From: Vladimir Vassilevsky on 4 Nov 2009 15:25

Compare exponents
Compare mantissas
What's a problem?

VLV


thunder wrote:

> Hi all
>
> I have a compute engine which generates an 8-bit floating number,
> fp_num[7:0]. The format of this 8-bit floating point number is 3-bit
> signed exponent and 5-bit mantissa (1-bit mantissa sign and 4-bit
> mantissa magnitude) ie
>
> 7 6 5 4 3
> 2 1 0
> exp exp exp mantissa_sign mantissa mantissa mantissa mantissa
>
>
> I need to make sure that the final value of fp_num i send out to the
> next block does not exceed the range [+num_clamp, -num_clamp], where
> num_clamp is also an 8-bit FP number with the same data bit
> representation as above, except the mantissa sign of num_clamp is
> always zero (ie the mantissa is always positive).
>
>
> One way i thought of doing this is to translate both fp_num and
> num_clamp to a fixed point number and then determine if fxd_num is
> less than or greater than fxd_num_clamp.
>
>
> I wondered if anyone has any other suggesstions to determine this
> floating point saturation, which might be simpler and/or better.
>
>
> Thanks in advance
>
> J
From: glen herrmannsfeldt on 4 Nov 2009 15:45
In comp.dsp Vladimir Vassilevsky <nospam(a)nowhere.com> wrote:

> Compare exponents
> Compare mantissas
> What's a problem?

Twice as much work as you need to do.

Note that the PDP-10 has one compare instruction for both
fixed and floating point numbers.

-- glen
From: Vladimir Vassilevsky on 4 Nov 2009 16:10


glen herrmannsfeldt wrote:

> In comp.dsp Vladimir Vassilevsky <nospam(a)nowhere.com> wrote:
>
>
>>Compare exponents
>>Compare mantissas
>>What's a problem?
>
>
> Twice as much work as you need to do.

Actually less of work. Both compare operations are narrow and could be
done in parallel. The question is likely in the context of FPGA.

> Note that the PDP-10 has one compare instruction for both
> fixed and floating point numbers.

This is possible if the floats are in IEEE754-like representation and
handling of NANs and denormals not required.

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com





From: thunder on 6 Nov 2009 04:32
On 4 Nov, 21:10, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote:
> glen herrmannsfeldt wrote:
> > In comp.dsp Vladimir Vassilevsky <nos...(a)nowhere.com> wrote:
>
> >>Compare exponents
> >>Compare mantissas
> >>What's a problem?
>
> > Twice as much work as you need to do.
>
> Actually less of work. Both compare operations are narrow and could be
> done in parallel. The question is likely in the context of FPGA.
>
> > Note that the PDP-10 has one compare instruction for both
> > fixed and floating point numbers.
>
> This is possible if the floats are in IEEE754-like representation and
> handling of NANs and denormals not required.
>
> Vladimir Vassilevsky
> DSP and Mixed Signal Design Consultanthttp://www.abvolt.com

The compares will be done in parallel.

Furthermore, the Floating numbers are internal representation and do
not conform to IEEE 754 representation. Thus handling of NANs and
denormals are not required.


Thanks


J
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