Terminate or not?
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From: Mr.G on 17 Mar 2010 08:59 Is there any rule of thumb which says whether digital traces need to be terminated or not? Specifically with QDRII and DDR2 memory interfaces where the trace length is likely to be max 50mm, and a clock speed of 250MHz. Thanks.
From: John Larkin on 17 Mar 2010 13:06 On Wed, 17 Mar 2010 12:59:30 -0000, "Mr.G" <nothere(a)hotmail.com> wrote: >Is there any rule of thumb which says whether digital traces need to be >terminated or not? >Specifically with QDRII and DDR2 memory interfaces where the trace length is >likely to be max 50mm, and a clock speed of 250MHz. >Thanks. > Edge rates matter more than frequency. A DDR2 interface can have sub-ns edges, so a 50 mm trace can ring. Some (all?) DDR2 drams have internal terminators that you can enable. I'd terminate all clock and control lines for sure; I think you can leave short data lines unterminated, but I'm not sure. There should be appnotes for both the dram chips and for whatever processor or FPGA you are using to talk to them. Ask at comp.arch.fpga, too. We recently did a Spartan6-to-DDR2 interface. It almost works. John
From: Grumps on 17 Mar 2010 13:31 "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message news:fm22q5t6b1kfaipu40me0ocgteuof7diol(a)4ax.com... > On Wed, 17 Mar 2010 12:59:30 -0000, "Mr.G" <nothere(a)hotmail.com> > wrote: > >>Is there any rule of thumb which says whether digital traces need to be >>terminated or not? >>Specifically with QDRII and DDR2 memory interfaces where the trace length >>is >>likely to be max 50mm, and a clock speed of 250MHz. >>Thanks. >> > > Edge rates matter more than frequency. A DDR2 interface can have > sub-ns edges, so a 50 mm trace can ring. Some (all?) DDR2 drams have > internal terminators that you can enable. I'd terminate all clock and > control lines for sure; I think you can leave short data lines > unterminated, but I'm not sure. There should be appnotes for both the > dram chips and for whatever processor or FPGA you are using to talk to > them. > > Ask at comp.arch.fpga, too. > > We recently did a Spartan6-to-DDR2 interface. It almost works. What part didn't work? Except for some TI DSP to DDR2 designs, I've always just terminated as I've had space to do so. This latest design is really tight on board space though.
From: Grumps on 17 Mar 2010 13:32 Sorry, yes I'm the OP. Different usernames on different PCs.
From: John Larkin on 17 Mar 2010 16:10
On Wed, 17 Mar 2010 17:31:39 -0000, "Grumps" <nothere(a)hotmail.com> wrote: >"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message >news:fm22q5t6b1kfaipu40me0ocgteuof7diol(a)4ax.com... >> On Wed, 17 Mar 2010 12:59:30 -0000, "Mr.G" <nothere(a)hotmail.com> >> wrote: >> >>>Is there any rule of thumb which says whether digital traces need to be >>>terminated or not? >>>Specifically with QDRII and DDR2 memory interfaces where the trace length >>>is >>>likely to be max 50mm, and a clock speed of 250MHz. >>>Thanks. >>> >> >> Edge rates matter more than frequency. A DDR2 interface can have >> sub-ns edges, so a 50 mm trace can ring. Some (all?) DDR2 drams have >> internal terminators that you can enable. I'd terminate all clock and >> control lines for sure; I think you can leave short data lines >> unterminated, but I'm not sure. There should be appnotes for both the >> dram chips and for whatever processor or FPGA you are using to talk to >> them. >> >> Ask at comp.arch.fpga, too. >> >> We recently did a Spartan6-to-DDR2 interface. It almost works. > >What part didn't work? The hard dram controller core is fairly brain-damaged. There's no way to clear the multiple command and data fifos, so it's hard to be sure what the state is. The only fix is to occasionally do a controller reset, which takes hundreds of microseconds and makes the timing analysis tools barf. We do seem to be able to read and write correctly. You can sort of see the FPGA-to-DRAM connections here: ftp://jjlarkin.lmi.net/Board51.jpg > >Except for some TI DSP to DDR2 designs, I've always just terminated as I've >had space to do so. This latest design is really tight on board space >though. > The chip we're using, MICRON MT47H64M16HR-3G, has internal terminators. John |