The Perfect Computer - 36 bits?
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From: Charles Shannon Hendrix on 6 Apr 2007 20:24 ["Followup-To:" header set to alt.folklore.computers.] > Actually, the really bad drivers come from US corporations, not > from China. Most Chinese companies have a mature and sensible > relationship to the drivers they ship. Yeah, they ship one buggy revision and never fix it... :) -- shannon "AT" widomaker.com -- ["There are nowadays professors of philosophy, but not philosophers." ]
From: krw on 6 Apr 2007 21:19 In article <m3abxlcaqt.fsf(a)garlic.com>, lynn(a)garlic.com says... > Del Cecchi <cecchinospam(a)us.ibm.com> writes: > > But they were considered separate sites, like POK and EF or POK and > > Kingston, at least in the part of IBM I was familiar with. > > re: > http://www.garlic.com/~lynn/2007g.html#47 The Perfect Computer - 36 bits? > > how, 'bout pok plant site and myers corner ... or former myers corner > ... just doing search engine, turns up > http://www.hvedc.com/siteadmin/upload/167-155MyersCornersRoad.pdf Wasn't Myers' Corner a 5XX building? ...making it a Fishkill location. ;-) > somewhat fading memory ... but i think sindelfingen and boeblingen were > closer than myers corners and pok plant site ... or closer than the > (former) san jose plant site and the (former) santa teresa lab (now > silicon valley lab). Fishkill to Poughkeepsie is less than 12 miles and Myers' Corners is inbetween (closer to Fishkill). > for total topic drift, i was on a trip in DC the week before they had > the opening ceremony for santa teresa lab. It had been originally going > to be called the Coyote lab (taking the name from the closest post > office) ... however, the week before, there was this demonstration on > the steps of the capital (i may have seen it, but was in no way part of > it) by the "Coyote" organization. They managed to quickly change the > name to santa teresa lab before the opening ceremony (after the closest > main road). -- Keith
From: Anne & Lynn Wheeler on 7 Apr 2007 11:34 Anne & Lynn Wheeler <lynn(a)garlic.com> writes: > the current feature that sometimes is referred to as possibly also being > leveraged for privacy invasive operations is the TPM/TCP/etc stuff for > trusted computing > > this thread/posts > http://www.garlic.com/~lynn/aadsm5.htm#asrn1 > http://www.garlic.com/~lynn/aadsm5.htm#asrn2 > http://www.garlic.com/~lynn/aadsm5.htm#asrn3 > http://www.garlic.com/~lynn/aadsm5.htm#asrn4 > > got started when I mentioned that I was giving a security/assurance talk > in the trusted computing track at an Intel Developers Conference. > > also reference here > http://www.garlic.com/~lynn/index.html#presentation > > this set of posts makes reference to a whole series of patents ... > some of them related to high assurance chip/device operation > http://www.garlic.com/~lynn/aadsm26.htm#48 Governance of anonymous financial services > http://www.garlic.com/~lynn/aadsm26.htm#49 Governance of anonymous financial services re: http://www.garlic.com/~lynn/2007g.html#61 The Perfect Computer - 36 bits? and for additional topic drift ... recent news URLs Forrester Research Questions the Future of NAC http://www.networkcomputing.com/channels/security/showArticle.jhtml?articleID=198800907 Forrester: Today's NAC is whack http://www.infoworld.com/article/07/04/05/HNforresternacdead_1.html NAC Attack: Today's Products Will Fail, Report Says http://www.eweek.com/article2/0,1895,2112120,00.asp What you need to know about NAC http://www.computerworld.com/action/article.do?command=viewArticleBasic&taxonomyId=16&articleId=9014179 .... so some of this about doing end-to-end authentication (including device authentication ... as per prior drift) could be consistent with ipsec from early 90s. I've contented that both SSL (from a little client/server startup) and VPNs both appeared about the same time ... in part prompted by the difficulty of adopting ipsec (and getting end-to-end low-level protocol authentication/security deployed in end-nodes). at '94 ietf meeting in san jose, somebody that we had worked with quite a bit, introduced VPN in the gateway working group (i.e. implemented in boundary routers). My view was that it resulted in some amount of consternation from the ipsec camp. It was semi-resolved when the ipsec camp took to calling VPN "lightweight" ipsec (which, in turn, sort-of met that regular ipsec was now "heavyweight" ipsec). VPN in boundary routers side-stepped the difficulty of deploying a lot of new security and authentication in low-level tcp/ip protocol stack (which typical also required a deploying new system/kernel for all the systems) for all the end-point systems. in the same period, SSL also appeared ... as an end-point to end-point solution ... but implemented in application layer ... again bypassing the difficulty related to low-level protocol and kernel change-over in large variety of end-point nodes. for other drift ... lots of past posts mentioning SSL http://www.garlic.com/~lynn/subpubkey.html#sslcert
From: Rich Alderson on 8 Apr 2007 23:16 So are you saying that VM/370 contained a table with all the serial numbers of all the 370-class CPUs ever sold by IBM (and others???)? Or was the table, as I surmise, one of model numbers to allow features to be based on what hardware is running? -- Rich Alderson | /"\ ASCII ribbon | news(a)alderson.users.panix.com | \ / campaign against | "You get what anybody gets. You get a lifetime." | x HTML mail and | --Death, of the Endless | / \ postings |
From: Anne & Lynn Wheeler on 9 Apr 2007 00:46
Rich Alderson <news(a)alderson.users.panix.com> writes: > So are you saying that VM/370 contained a table with all the serial > numbers of all the 370-class CPUs ever sold by IBM (and others???)? > Or was the table, as I surmise, one of model numbers to allow features > to be based on what hardware is running? re: http://www.garlic.com/~lynn/2007g.html#54 The Perfect Computer - 36 bits? http://www.garlic.com/~lynn/2007g.html#55 IBM to the PCM market http://www.garlic.com/~lynn/2007g.html#56 The Perfect Computer - 36 bits? http://www.garlic.com/~lynn/2007g.html#61 The Perfect Computer - 36 bits? as before ... the store cpuid has several parts ... the processor model or processor type ... i.e. like 135, 145, 155, 165, 138, 148, 158, 168, etc ... and the processor serial number ... which could be used for licensing software for a specific processor ... and then some number of other things vm370 kernel had table of processor numbers ... 135, 145, 155, 165, 138, 148. 158, 168 ... etc ... with some kernel processing parameters specific to that processor. at startup, the kernel would execute the store cpuid ... and then look up the model number (part, not the processor serial number part) in the processing table. the first post has URL pointer to specification and features of the store cpuid instruction http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR003/10.58?SHELF=DZ9ZBK03&DT=20040504121320 so new/updated kernels needed to be shipped when new processor models came out. also there were some issues regarding processors shipped by the clone vendors ... which would have different values for the cpuid. what i was describing was the resource manager product that i shipped replacing the processor model table with other code that more dynamically determined processor specific characteristic processing (and eliminated the processor model table and the associated code). the addition of ECPS support to the vm370 kernel presented a different, but similar type of processor specific adaptation. recent post mentioning ECPS http://www.garlic.com/~lynn/2007g.html#44 1960s: IBM mgmt mistrust of SLT for ICs? Some amount of ECPS was the migration of 370 kernel instructions into the machine (138/148) microcode. The 138/148 microcode avg. about ten micro-instructions for every 370 instruction. The kernel 370 instructions migrated into machine microcode at nearly one-for-one (i.e. one kernel 370 instruction converted almost directly into a single microcode instruction) ... resulting in nearly 10:1 performance increase. The methodology of this part of ECPS was to define a new "370" instruction that was placed in front of the sequence of kernel instructions that it was "replacing". The new instruction would invoke microcode that exactly implemented the corresponding kernel instruction sequence. The arguments to each of these new instructions included a parameter list ... one of the items in the parameter list was the 370 instruction to resume normal kernel 370 instruction execution (it would appear as if each of the new instructions did a whole bunch of function and then "branched" around all the instructions that it was replacing). The issue now is what does the kernel do if it boots on a machine that didn't implement all the new ECPS instructions. In this case, the initial kernel boot (w/ECPS support) checks to see whether or not the processor has ECPS support and whether the ECPS "level" corresponds to the "level" of the booted kernel ... if either of these aren't true .... the initial boot has a table of the location of every ECPS instruction in the kernel ... and runs thru the table overlaying every ECPS instruction with 370 "no-op". Another part of ECPS was taking the microcode for some of the "privilege" instructions and implementing support ... so the microcode implementation includes support for both privilege mode and virtual machine privilege mode. This avoids the interrupt into the kernel for software simulation of the virtual machine privilege instruction. The ECPS one-for-one instruction replacement worked well on the low and mid-range 370s (something like 10:1 performance improvement) ... but provided little or no benefit on the high-end 370 processors ... which were started to do 370 instructions in one instruction per machine cycle. In fact, attempting the one-for-one replacement strategy on the high-end 370s could even result in performance degradation for one reason or another. slightly related post http://www.garlic.com/~lynn/2007g.html#59 IBM to the PCM market Eventually for the high-end processors, the "SIE" instruction was introduced ... which was a more complete formalization of "virtual machine mode" support for privilege instructions. This was somewhat what subsequently grew into PR/SM hypervisor mode and the current LPAR support. a couple past posts mentioning SIE http://www.garlic.com/~lynn/94.html#37 SIE instruction (S/390) http://www.garlic.com/~lynn/2000b.html#50 VM (not VMS or Virtual Machine, the IBM sort) http://www.garlic.com/~lynn/2000b.html#51 VM (not VMS or Virtual Machine, the IBM sort) http://www.garlic.com/~lynn/2000b.html#52 VM (not VMS or Virtual Machine, the IBM sort) http://www.garlic.com/~lynn/2001b.html#29 z900 and Virtual Machine Theory http://www.garlic.com/~lynn/2001g.html#21 Root certificates http://www.garlic.com/~lynn/2001h.html#71 IBM 9020 FAA/ATC Systems from 1960's http://www.garlic.com/~lynn/2001h.html#73 Most complex instructions http://www.garlic.com/~lynn/2001m.html#38 CMS under MVS http://www.garlic.com/~lynn/2001m.html#53 TSS/360 http://www.garlic.com/~lynn/2002b.html#6 Microcode? http://www.garlic.com/~lynn/2002b.html#44 PDP-10 Archive migration plan http://www.garlic.com/~lynn/2002o.html#15 Home mainframes http://www.garlic.com/~lynn/2002o.html#18 Everything you wanted to know about z900 from IBM http://www.garlic.com/~lynn/2002p.html#40 Linux paging http://www.garlic.com/~lynn/2002p.html#44 Linux paging http://www.garlic.com/~lynn/2002p.html#48 Linux paging http://www.garlic.com/~lynn/2003.html#5 vax6k.openecs.org rebirth http://www.garlic.com/~lynn/2003.html#6 vax6k.openecs.org rebirth http://www.garlic.com/~lynn/2003.html#7 vax6k.openecs.org rebirth http://www.garlic.com/~lynn/2003b.html#0 Disk drives as commodities. Was Re: Yamhill http://www.garlic.com/~lynn/2003f.html#54 ECPS:VM DISPx instructions http://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions http://www.garlic.com/~lynn/2003j.html#42 Flash 10208 http://www.garlic.com/~lynn/2003n.html#13 CPUs with microcode ? http://www.garlic.com/~lynn/2003o.html#52 Virtual Machine Concept http://www.garlic.com/~lynn/2005e.html#57 System/360; Hardwired vs. Microcoded http://www.garlic.com/~lynn/2006.html#17 {SPAM?} DCSS as SWAP disk for z/Linux http://www.garlic.com/~lynn/2006c.html#9 Mainframe Jobs Going Away http://www.garlic.com/~lynn/2006j.html#27 virtual memory http://www.garlic.com/~lynn/2006j.html#29 How to implement Lpars within Linux http://www.garlic.com/~lynn/2006j.html#31 virtual memory http://www.garlic.com/~lynn/2006l.html#22 Virtual Virtualizers http://www.garlic.com/~lynn/2006n.html#44 Any resources on VLIW? http://www.garlic.com/~lynn/2006p.html#42 old hypervisor email http://www.garlic.com/~lynn/2007b.html#1 How many 36-bit Unix ports in the old days? http://www.garlic.com/~lynn/2007b.html#21 history question http://www.garlic.com/~lynn/2007c.html#49 SVCs http://www.garlic.com/~lynn/2007d.html#61 ISA Support for Multithreading http://www.garlic.com/~lynn/2007d.html#65 IBM S/360 series operating systems history http://www.garlic.com/~lynn/2007e.html#39 FBA rant |