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From: ChrisQ on 31 Oct 2009 12:29 nmm1(a)cam.ac.uk wrote: > Yes, but I wasn't cheating in that way - the machine I used did NOT > memory map registers - it had 128 registers, and used a special > register to allow register indexing. > 128 registers provides a bit more space then the pdp11's 8, but how did your code work ?. The registers must have been sequential in some accessable address space for the program counter to access them, or you were doing something really clever like indirect execution through the index ?. Not familiar with that architecture makes it more difficult guess. Just how did it work ? :-)... Regards, Chris
From: Terje Mathisen on 31 Oct 2009 14:32 On Oct 31, 6:17 am, Brett Davis <gg...(a)yahoo.com> wrote: > http://en.wikipedia.org/wiki/RRAMhttp://en.wikipedia.org/wiki/Memristor > > Look at that die picture, I am not talking 6 transistor SRAM, this has > no transistors. Makes a 6 transistor SRAM look like a vacuum tube, at > ~25 times smaller. All the transistors are in the bottom layer, this can > be put on any layer. Quoted 100 gigabits per chip, I am assuming 1 > square centimeter, and assuming 22nm, and then rounded down to get 8 > gigaBYTES. That's bogus. According to the same wiki link, there's no way to switch state quickly for that memristor, due to very low mobility. The testing described was at ~1Hz, which is a few orders of magnitude below what you need for useful performance. I.e. this might well work at some point in time, but not in "2-4 years", more like 10-20. :-( Terje (who'd love to have a GB or so of embedded RAM/core. :-)
From: ChrisQ on 31 Oct 2009 19:24 nmm1(a)cam.ac.uk wrote: > In article <vxXGm.23512$nI.4033(a)newsfe14.ams2>, > ChrisQ <meru(a)devnull.com> wrote: >>> There always have been applications that need a limited working >>> set. I once wrote a serious application that ran almost entirely >>> in a CPU's registers - all right, that was a Ferranti Atlas/Titan :-) >> You could do that on some of the early pdp11's, which had all the >> registers mapped into address space. The example I remember was a >> simple core memory test program and may have been in one of the 11/05 >> manuals. > > Yes, but I wasn't cheating in that way - the machine I used did NOT > memory map registers - it had 128 registers, and used a special > register to allow register indexing. > > > Regards, > Nick Maclaren. Looks like it's already been done. Have you seen this ?.. http://www.tilera.com/products/TILE-Gx.php A load of supporting software and development hardware platforms as well... Regards, Chris
From: nmm1 on 1 Nov 2009 05:26 In article <vBZGm.2971$6O1.1139(a)newsfe08.ams2>, ChrisQ <meru(a)devnull.com> wrote: > >> Yes, but I wasn't cheating in that way - the machine I used did NOT >> memory map registers - it had 128 registers, and used a special >> register to allow register indexing. > >128 registers provides a bit more space then the pdp11's 8, but how did >your code work ?. The registers must have been sequential in some >accessable address space for the program counter to access them, or you >were doing something really clever like indirect execution through the >index ?. Not familiar with that architecture makes it more difficult guess. > >Just how did it work ? :-)... After 40+ years, I should have to check up on which algorithm it was and reinvent the method. Basically, it was something that needed a lot of combinatoric calculations on a small number of counts. And, yes, you could index through the registers. The loading and unloading was manual, of course. Regards, Nick Maclaren.
From: Bernd Paysan on 1 Nov 2009 19:28
Terje Mathisen wrote: > That's bogus. > > According to the same wiki link, there's no way to switch state > quickly for that memristor, due to very low mobility. > > The testing described was at ~1Hz, which is a few orders of magnitude > below what you need for useful performance. If I recall correctly, the CNT with embedded iron shuttles is "good enough" if you want hard-disk-like writes, but probably "orders of magnitude too low" if you want DRAM-like writes (although the write speed scales exponentially with voltage, so probably you just have to go high enough with the write voltage). I would expect that memristors will first be used as flash-like memories (essentially hard-disks), until we find memristors fast enough to be used as main memory. Hm, digging out the publication leads me here: http://www.physics.berkeley.edu/research/zettl/pdf/361.NanoLet.9- Begtrup.pdf > I.e. this might well work at some point in time, but not in "2-4 > years", more like 10-20. I don't think one can plan the availability of unobtanium. The current state of research is to find a material that is suitable as memristor. You can find one tomorrow, or not in 1000 years. Zettl's nanotubes with embedded iron shuttles look much better than HPs titanium dioxide memristors. They are also probably a lot harder to make ;-). -- Bernd Paysan "If you want it done right, you have to do it yourself" http://www.jwdt.com/~paysan/ |