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From: Maurice Branson on 26 Mar 2010 06:18
"Andrew Jackson" <alj(a)nospam.com> wrote
news:X_adnaUfiO556jHWnZ2dnUVZ8l2dnZ2d(a)eclipse.net.uk...

> ways, you would be better doing a USB2.0 device and sticking on a suitable
> USB PHY for the physical interface. There aren't many USB 3.0 hosts
> around yet against which you could test your device either: lots

Thanks, Andrew!

Sounds resonable to me. So if I start with 2.0 is there a compatibility that
I may "expand" my design to a 3.0 core or is it totally different? I learned
from what I've read here and in the www that I need at least a separate PHY
because that is something that I cannot to in the FPGA fabric. Are there any
USB 3.0 PHYs already available? Found nothing. :-(

KR Maurica


From: wojtek on 26 Mar 2010 07:30
On Mar 26, 11:18 am, "Maurice Branson" <trauben...(a)arcor.de> wrote:
> "Andrew Jackson" <a...(a)nospam.com> wrotenews:X_adnaUfiO556jHWnZ2dnUVZ8l2dnZ2d(a)eclipse.net.uk...
>
> > ways, you would be better doing a USB2.0 device and sticking on a suitable
> > USB PHY for the physical interface.  There aren't many USB 3.0 hosts
> > around yet against which you could test your device either: lots
>
> Thanks, Andrew!
>
> Sounds resonable to me. So if I start with 2.0 is there a compatibility that
> I may "expand" my design to a 3.0 core or is it totally different? I learned
> from what I've read here and in the www that I need at least a separate PHY
> because that is something that I cannot to in the FPGA fabric. Are there any
> USB 3.0 PHYs already available? Found nothing. :-(
>
> KR Maurica

3.0 core is basically separate from 2.0 on almost every layer, if you
have a usb 3.0 device it tries to connect using super speed and if
that is not available on the other side, the 3.0 core shuts down and
2.0/1.1 core starts its operation. The PHY is not publicly available,
because there is no market for it, right now only big companies
working on usb 3.0 appliances (like WD, Samsung, Intel, ...) have it
available.
From: Antti on 26 Mar 2010 08:58
On Mar 26, 1:30 pm, wojtek <wojtekpowiertow...(a)gmail.com> wrote:
> On Mar 26, 11:18 am, "Maurice Branson" <trauben...(a)arcor.de> wrote:
>
> > "Andrew Jackson" <a...(a)nospam.com> wrotenews:X_adnaUfiO556jHWnZ2dnUVZ8l2dnZ2d(a)eclipse.net.uk...
>
> > > ways, you would be better doing a USB2.0 device and sticking on a suitable
> > > USB PHY for the physical interface.  There aren't many USB 3.0 hosts
> > > around yet against which you could test your device either: lots
>
> > Thanks, Andrew!
>
> > Sounds resonable to me. So if I start with 2.0 is there a compatibility that
> > I may "expand" my design to a 3.0 core or is it totally different? I learned
> > from what I've read here and in the www that I need at least a separate PHY
> > because that is something that I cannot to in the FPGA fabric. Are there any
> > USB 3.0 PHYs already available? Found nothing. :-(
>
> > KR Maurica
>
> 3.0 core is basically separate from 2.0 on almost every layer, if you
> have a usb 3.0 device it tries to connect using super speed and if
> that is not available on the other side, the 3.0 core shuts down and
> 2.0/1.1 core starts its operation. The PHY is not publicly available,
> because there is no market for it, right now only big companies
> working on usb 3.0 appliances (like WD, Samsung, Intel, ...) have it
> available.

well, USB 3.0 is the first one that needs NO PHY

as the MGT's in some newer FPGA's are USB 3.0 capable directly
just wire MGT to usb 3.0 superspeed pins, and that about it

Antti

From: wojtek on 26 Mar 2010 09:32
On Mar 26, 1:58 pm, Antti <antti.luk...(a)googlemail.com> wrote:
> well, USB 3.0 is the first one that needs NO PHY
>
> as the MGT's in some newer FPGA's are USB 3.0 capable directly
> just wire MGT to usb 3.0 superspeed pins, and that about it
>
> Antti

That is the first time i hear abou MGT being compatible with USB 3.0
PHY, but I haven't doing anything in USB 3.0 topic for almost a year.
I must say I find it hard to believe thought, because USB 3.0 besides
translating digital signal to differential analog signal also
transmits USB 3.0 specific LFPS (low frequency pulse signaling) and
from what I learned the USB 3.0 PHY was supposed to take care of that
(just like latest PCI express PHY, which has similar LFPS technology).
I believe the MGT doesn't support that. But as I've said I hadn't even
researched it for some time, so I might be wrong.
From: luudee on 29 Mar 2010 00:30
On Mar 26, 8:32 pm, wojtek <wojtekpowiertow...(a)gmail.com> wrote:
> On Mar 26, 1:58 pm, Antti <antti.luk...(a)googlemail.com> wrote:
>
> > well, USB 3.0 is the first one that needs NO PHY
>
> > as the MGT's in some newer FPGA's are USB 3.0 capable directly
> > just wire MGT to usb 3.0 superspeed pins, and that about it
>
> > Antti
>
> That is the first time i hear abou MGT being compatible with USB 3.0
> PHY, but I haven't doing anything in USB 3.0 topic for almost a year.
> I must say I find it hard to believe thought, because USB 3.0 besides
> translating digital signal to differential analog signal also
> transmits USB 3.0 specific LFPS (low frequency pulse signaling) and
> from what I learned the USB 3.0 PHY was supposed to take care of that
> (just like latest PCI express PHY, which has similar LFPS technology).
> I believe the MGT doesn't support that. But as I've said I hadn't even
> researched it for some time, so I might be wrong.


USB 3.0 calls the "LFPS" now "OOB". Xilinx GTX transceivers have no
problem supporting that. Matter of fact we have a fully working USB
3.0
device IP Core running on Xilinx FPGAs.

One more note to the OP: In order to properly implement USB 3.0, you
would most likely need a protocol analyser, roughly a $50K
investment ...

Cheers,
rudi

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